BS62LV256 Brilliance Semiconductor, BS62LV256 Datasheet - Page 7

• Manufacturer Part Number: BS62LV256
• Description: Very Low Power/Voltage CMOS SRAM 32K X 8 bit
• Manufacturer: Brilliance Semiconductor

R0201-BS62LV256
WRITE CYCLE2
ADDRESS
CE
WE
D
D
IN
OUT
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
3. T
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
6. OE is continuously low (OE = V
7.
8. D
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
10. Transition is measured
11. T
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
to the outputs must not be applied.
transition, output remain in a high impedance state.
opposite phase to the outputs must not be applied to them.
D
The parameter is guaranteed but not 100% tested.
WR
OUT
OUT
CW
is measured from the earlier of CE or WE going high at the end of write cycle.
BSI
is the read data of next address.
is measured from the later of CE going low to the end of write.
is the same phase of write data of this write cycle.
(1,6)
±
500mV from steady state with C
t
AS
IL
).
(5)
t
(4,10)
WHZ
t
AW
t
t
t
7
CW
WC
WP
(11)
(2)
L
= 5pF as shown in Figure 1B.
t
DW
t
DH
(8,9)
t
(7)
DH
BS62LV256
(8)
Revision 2.2
April 2001