AK4640VG Asahi Kasei Microsystems, AK4640VG Datasheet - Page 66

• Manufacturer Part Number: AK4640VG
• Description: 16BIT CODEC WITH MIC /HP/SPK-AMPl
• Manufacturer: Asahi Kasei Microsystems

ASAHI KASEI
MS0273-E-00
External MCLK
(Addr:04H, D5-4)
BICK, LRCK
3. When an external clock is used in PLL mode. (Slave mode)
<Example>
(Addr:01H, D7)
(Addr:01H, D5)
(Addr:04H, D3)
MCKPD bit
PS1-0 bits
PMPLL bit
MCKO pin
MCKO bit
(Slave Mode)
(1) Release the pull-down of the XTI pin : MCKPD bit = “1” → “0”
(2) Input an external MCKI
(3) Power-up PLL : PMPLL bit = “0” → “1”
(4) Enable MCKO output : MCKO bit = “0” → “1”
(5) MCKO is output after PLL lock time.
(6) Input BICK and LRCK that synchronized in the MCKO output.
(7) Set up MCKO output frequency (PS1-0 bits)
PLL needs 40ms lock time after the PMPLL bit = “0” → “1”.
If PS1-0 bits are changed before LRCK is input, MCKO is not output. PS1-0 bits should be changed after
LRCK is input.
(1)
(2)
(3)
(4)
00
40ms(max)
Figure 47. Clock Set Up Sequence(3)
Input
(5)
(6)
- 66 -
Output
(7)
Input
XX
E xam p le :
A u d io I/F F o r m a t : I
B IC K f re q u e nc y a t M a s te r M o d e : 6 4 f s
I np u t M a s t e r C lo c k S e le c t a t P L L M o d e : 1 1 .2 8 9 6 M H z
O utp u t M a s te r C lo c k F re q ue n c y : 6 4 f s
(6 ) B IC K a nd L R C K inp u t s ta rt
(1 ) A d d r:0 1 H , D a ta :0 0 H
(2 ) In pu t exte rn a l M C L K
(3 ) A d d r:0 1 H , D a ta 2 0 H
(4 ) A d d r:0 4 H , D a ta 4 A H
(5 ) M C K O ou tp u t starts
(7 ) A d d r:0 4 H , D a ta 6 A H
2
S
[AK4640]
2004/03