ML7000-01 OKI electronic componets, ML7000-01 Datasheet - Page 5

• Manufacturer Part Number: ML7000-01
• Description: Single Rail CODEC
• Manufacturer: OKI electronic componets

V
Power supply for +5 V (ML7000-xx) or +3 V (ML7001-xx)
PCMIN
PCM data input.
A serial PCM data input to this pin is converted to an analog signal in synchronization with the
The data rate of PCM is equal to the frequency of the BCLK signal.
PCM signal is shifted in at the falling edge of the BCLK signal and latched into the internal
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
BCLK
Shift clock signal input for the PCMIN and PCMOUT signals.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, or 2048
¡ Semiconductor
PWI, AOUT+, AOUT–
PWI is connected to the inverting input of the receive driver.
The receive driver output is connected to the AOUT– pin. Therefore, the receive level can be
adjusted with the pins VFRO, PWI, and AOUT–. During power-saving or power down-mode,
the outputs of AOUT+ and AOUT– are in a high impedance state. The output of AOUT+ is
inverted with respect to the output of AOUT–. Since these outputs provide differential drive of
an impedance of 1.2 kW, they can directly be connected to a handset using a piezoelectric
earphone or a line transformer. Refer to the application example.
RSYNC signal and BCLK signal.
register when shifted by eight bits.
kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power
saving state.
DD
20 kW
SG
SG
Receive filter
–
+
–
+
20 kW
AOUT–
AOUT+
VFRO
PWI
R6
VI
R7
VO
ZL
ML7000-01/02/03/ML7001-01/02/03
R6 > 20 kW
ZL > 1.2 kW
Gain = VO/VI = 2 5 R7/R6 £ 2
5/19