AM79C989JCT Advanced Micro Devices, AM79C989JCT Datasheet - Page 14

• Manufacturer Part Number: AM79C989JCT
• Description: Quad Ethernet Switching Transceiver (QuEST)
• Manufacturer: Advanced Micro Devices

10BASE-T Receiver
The 10BASE-T interface section includes a compliant
10BASE-T receiver which incorporates a low pass filter
eliminating the requirement for off-chip filters. The re-
ceiver circuit employs squelch circuits programmable
to a standard distance of 100 meters and an extended
distance mode for distances greater than 100 meters.
The squelch circuit requires that the differential receive
data on RXD exceed the squelch levels on both neg-
ative and positive pulses and occur in a consecutive
negative, positive, negative sequence.
There are restrictions on the frequency and pulse width
duration. If all conditions are met, the receiver will tran-
sition to the unsquelch state, which indicates that a
10BASE-T carrier is detected. If either the voltage lev-
els drop below a defined minimum or the frequency of
the incoming waveform drops below a set minimum,
the squelch circuit will indicate that the carrier is no
longer present. When the carrier is dropped, the
squelch circuit will return to the squelched state.
In order for an incoming Ethernet frame to be received
on the 10BASE-T receive pair, the frame must first
pass the receive squelch levels. The received
Manchester data is then forwarded to the Manchester
decoder. The Manchester decoder extracts the clock
and receive data from the Manchester data stream and
forwards the data to the elasticity FIFO. The sole pur-
pose of the elasticity FIFO is to rate match the receive
data to the synchronous system clock, SCLK. The data
which is output from the elasticity FIFOs is combined in
the serial multiplexer logic and output in a serially mul-
tiplexed format through the QuASI Interface.
In addition to detecting a 10BASE-T carrier, the re-
ceiver detects valid link pulses. Valid link pulses must
pass the squelch level amplitude, but must not be too
short or too long in duration. If link pulses are detected,
this information is passed to the Link Integrity and Auto-
Negotiation logic.
Once in the unsquelched state, the receiver amplifies
the differential signal to full CMOS levels for Manches-
ter clock and data extraction.
Differential Receiver
The differential receiver accepts data in differential for-
mat. The receiver has internal filtering and does not re-
quire external filters. The RXD receive pair require a
100-
inputs. The RXD inputs are internally biased to approx-
imately 3 V. When properly terminated, the RXD ports
will satisfy the electrical requirements for 10BASE-T
receivers in the EEE 802.3i standard.
Receive Polarity Correction
The receive function includes the ability to invert the
polarity of the signals appearing at the RXD pair if the
14
(1% tolerance) termination resistor across their
P R E L I M I N A R Y
Am79C989
polarity of the received signal is reversed, (e.g., wiring
error in cable). The polarity correction can be disabled
by setting Bit 3 of the Control Register (Reg 18). The
polarity detection function is activated following Reset
or Link Fail and will reverse the receive polarity based
on both link pulses and subsequent received frames
with a valid End of Transmit Delimiter (ETD).
When in the Link Fail State, the QuEST device will rec-
ognize link test pulses of either positive or negative po-
larity. Exit from the Link Fail state is caused by the
reception of five consecutive link pulses of identical po-
larity. The polarity of both the link pulses and the ETD
character of valid frames are used to determine the ini-
tial receive polarity. Once two consecutive frames are
received with the same polarity, the polarity function is
locked until a reset or link failure occurs.
Extended Distance
The receive squelch thresholds can be programmed to
60 percent of the normal level to allow reception of valid
10BASE-T receive frames over distances longer than
100 meters of cable. Normal operation (default) of the
QuEST device is set to standard 10BASE-T thresholds.
Extended distance mode is programmed by setting
Control Register (Reg. 18, bit 1).
Collision
When a valid receive frame is detected by unsquelch-
ing the input receiver and there is simultaneous activity
of the TXD pairs, a collision is detected and indicated
at the QuASI interface by assertion of the QCLSN sig-
nal during the appropriate channel slot time.
The QCLSN signal can be asserted for two other con-
ditions. If the SQE_TEST disable bit, Control Register
(Reg. 18, bit 0) is de-asserted, the QCLSN signal will
be asserted just after transmission of a valid frame dur-
ing the SQE window. If the 10BASE-T transmitter is in
the Jabber state, the QCLSN signal will be asserted
during the channel slot time if the QTX_EN enable sig-
nal is asserted for that channel.
When the QuEST device is in full duplex mode, no col-
lision events are indicated.
Link Integrity with Auto-Negotiation
General
The QuEST device can be configured to support either
the standard 10BASE-T link integrity algorithm as
specified in the IEEE 802.3i Standard or the Auto-Ne-
gotiation algorithm as specified in the IEEE 802.3u
standard. Auto-Negotiation allows the device to auto-
matically negotiate to full duplex operation if the remote
device at the end of the cable supports full duplex op-
eration. Remote Fault and Next Page are also sup-
ported. If the remote device does not support Auto-
Negotiation, the algorithm defaults to the standard
10BASE-T algorithm.