LRS13023 Sharp, LRS13023 Datasheet - Page 12

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LRS13023

Manufacturer Part Number
LRS13023
Description
Stacked Chip 8M Flash and 1M SRAM
Manufacturer
Sharp
Datasheet
~Individual
‘sixteen block lock-bits
land unlock blocks. Block lock-bits gate block erase and
‘byte write operations,
~block lock-bit
loperations
The status register
The access time is 130 ns (tAvQv) over the commercial
voltage range of 2.7V-3.6V.
and Clear Block Lock-Bits
lock-bits.
erase, byte write, or lock-bit configuration
finished.
temperature
SHARP
block locking
(Set Block Lock-Bit,
range (-40°C to +BS’C) and V,,
modification.
indicates
while the master lock-bit
and a master lock-bit,
uses a combination
commands)
when the WSM’s
Lock-bit
Set Master
4 x :
occcdc.r
set and cleared
configuration
.
.
operation
Lock-Bit,
Figure 1. Block Diagram
of bits,
to lock
supply
block
LRS13023
gates
is
64KByle
BlOCb
16
The
substantially
in static mode (addresses not switching).
When a
standby mode is enabled. When the RP pin is at GND,
deep power-down
power
during
switching
device has a wake time (tpHEL) from m-high
writes to the CUI are recognized.
WSM is reset and the status register is cleared.
Automatic
reset. A reset time (tPHqv) is required
consumption
high until outputs
and RF pins are at V,,,
reduces active current when the device is
mode is enabled which minimizes
Power
and provides
Savings
are valid. Likewise,
With RP at GND, the
write
(AI%)
the I,,
protection
from RP
feature
CMOS
until
the
10

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