K4S641632E Samsung semiconductor, K4S641632E Datasheet - Page 2

• Manufacturer Part Number: K4S641632E
• Description: 64Mbit SDRAM
• Manufacturer: Samsung semiconductor

1M x 16Bit x 4 Banks Synchronous DRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the system
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
FUNCTIONAL BLOCK DIAGRAM
K4S641632E
clock
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
ADD
CLK
LCKE
*
CLK
Samsung Electronics reserves the right to change products or specification without notice.
LRAS
CKE
Bank Select
LCBR
CS
LWE
RAS
Timing Register
LCAS
CAS
ORDERING INFORMATION
GENERAL DESCRIPTION
rate Dynamic RAM organized as 4 x 1,048,576 words by 16
bits, fabricated with SAMSUNG s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programma-
ble burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
K4S641632E-TC50/TL50
K4S641632E-TC55/TL55
K4S641632E-TC60/TL60
K4S641632E-TC70/TL70
K4S641632E-TC75/TL75
K4S641632E-TC1H/TL1H 100MHz(CL=2)
K4S641632E-TC1L/TL1L
The K4S641632E is 67,108,864 bits synchronous high data
Latency & Burst Length
Programming Register
WE
Data Input Register
Column Decoder
1M x 16
1M x 16
1M x 16
1M x 16
Part No.
L(U)DQM
LWCBR
200MHz(CL=3)
183MHz(CL=3)
166MHz(CL=3)
143MHz(CL=3)
133MHz(CL=3)
100MHz(CL=3)
Max Freq.
Rev.0.2 Sept. 2001
CMOS SDRAM
LDQM
Interface Package
LVTTL
LWE
LDQM
DQi
TSOP(II)
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