HYS64D16000GU-8-A Infineon, HYS64D16000GU-8-A Datasheet - Page 24

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HYS64D16000GU-8-A

Manufacturer Part Number
HYS64D16000GU-8-A
Description
Unbuffered DDR SDRAM-Modules
Manufacturer
Infineon
Datasheet
Table 11
Byte#
26
27
28
29
30
31
32
33
34
35
36 to 40
41
42
43
44
45
46 to 61
62
63
64
65 to 71
72
73 to 90
91 to 92
93 to 94
95 to 98
99 to 127
128 to 255 open for Customer use
Data Sheet
Description
Access Time from Clock at
CL = 1.5
Minimum Row Precharge
Time
Minimum Row Act. to Row
Act. Delay
Minimum RAS to CAS Delay
t
Minimum RAS Pulse Width
t
Module Bank Density (per
Bank)
Addr. and Command Setup
Time
Addr. and Command Hold
Time
Data Input Setup Time
Data Input Hold Time
Superset Information
Minimum Core Cycle Time
t
Min.
Cycle Time
Maximum Clock Cycle Time
t
Max. DQS-DQ Skew tDQSQ 0.6 ns
X-Factor tQHS
Superset Information
SPD Revision
Checksum for Bytes 0 - 62
Manufactures
Codes
Manufactures
Module Assembly Location
Module Part Number
Module Revision Code
Module Manufacturing Date
Module Serial Number
SPD Codes for PC1600 Modules -8 (cont’d)
RCD
RAS
RC
CK
Auto
t
RRD
t
FRC
Refresh
JEDEC
Cmd
ID
not supported
20 ns
15 ns
20 ns
50 ns
128 MByte
1.1 ns
1.1 ns
0.6 ns
0.6 ns
70 ns
80 ns
12 ns
1.0 ns
Revision 0.0
24
HYS[64/72]D[16000/32020]GU-[7/8]-A
128MB
x64
1rank
–8
hex.
00
50
3C
50
32
20
B0
B0
60
60
46
50
30
3C
A0
00
00
84
Infineon
Unbuffered DDR SDRAM-Modules
128MB
x72
1rank
–8
hex.
00
50
3C
50
32
20
B0
B0
60
60
46
50
30
3C
A0
00
00
96
Infineon
128MB
x64
2ranks
–8
hex.
00
50
3C
50
32
20
B0
B0
60
60
46
50
30
3C
A0
00
00
85
Infineon
10292003-WLD7-IJ5Z
Rev. 1.03, 2004-01
SPD Contents
128MB
x64
2ranks
–8
hex.
00
50
3C
50
32
20
B0
B0
60
60
46
50
30
3C
A0
00
00
97
Infineon

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