HYS64D16301GU-6-C Infineon, HYS64D16301GU-6-C Datasheet - Page 24

• Manufacturer Part Number: HYS64D16301GU-6-C
• Description: 184-Pin Unbuffered Double Data Rate SDRAM
• Manufacturer: Infineon

Table 17
Parameter
Active to Active/Auto-refresh command
period
Auto-refresh to Active/Auto-refresh
command period
Active to Read or Write delay
Precharge command period
Active to Autoprecharge delay
Active bank A to Active bank B command
Write recovery time
Auto precharge write recovery + precharge
time
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
1) 0 °C ≤
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
4) Inputs are not recognized as valid until
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7)
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
11) For each of the terms, if not already an integer, round to the next highest integer.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
(DDR400)
level for signals other than CK/CK, is
t
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
system performance (bus turnaround) degrades accordingly.
measured between
cycle time.
HZ
and
T
t
LZ
A
AC Timing - Absolute Specifications for PC3200 and PC2700 (cont’d)
≤ 70 °C
transitions occur in the same access time windows as valid data transitions. These parameters are not referred
; V
V
DDQ
IH(ac)
= 2.5 V ± 0.2 V,
and
V
IL(ac)
.
V
REF
V
REF
. CK/CK slew rate are ≥ 1.0 V/ns.
V
DD
stabilizes.
Symbol –6
t
t
t
t
t
t
t
t
t
t
t
t
RC
RFC
RCD
RP
RAP
RRD
WR
DAL
WTR
XSNR
XSRD
REFI
= +2.5 V ± 0.2 V (DDR333);
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
DDR333
Min.
60
72
18
18
t
12
15
(t
1
75
200
—
RCD
24
WR
/t
or t
CK
Max.
)+(t
—
—
—
—
—
—
—
—
—
7.8
RASmin
RP
/t
CK
Unbuffered DDR SDRAM Modules
) (t
–5
DDR400B
Min.
V
55
70
15
15
t
10
15
2
75
200
—
RCD
DDQ
WR
/t
or t
= 2.6 V ± 0.1 V,
t
CK
CK
)+(t
Max.
RASmin
—
—
—
—
—
—
—
—
—
7.8
is equal to the actual system clock
RP
t
DQSS
Electrical Characteristics
/t
CK
.
)
Unit Note/ Test
ns
ns
ns
ns
ns
ns
ns
t
t
ns
t
µs
V
CK
CK
CK
DD
Rev. 1.0, 2004-03
= +2.6 V ± 0.1 V
Condition
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)11)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)12)
V
1)
TT
.