GS82032 ETC, GS82032 Datasheet - Page 17

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GS82032

Manufacturer Part Number
GS82032
Description
64K x 32 2M Synchronous Burst SRAM
Manufacturer
ETC
Datasheet

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Rev: 1.09 7/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Pipelined SCD Read Cycle Timing
BW
DQ
A
A
–BW
ADSC
ADSP
–DQ
ADV
GW
BW
CK
A
E
E
E
D
G
D
n
1
2
3
Hi-Z
tS
tS tH
tS tH
tS
tS
Single Read
RD1
tH
tH
tH
tOLZ
tLZ
tS
tS
tS
tH
tKQ
tOE
tS tH
RD2
Q1
E
2
tKH
17/23
and E
A
tOHZ
tKL
3
only sampled with ADSP or ADSC
Burst Read
tKC
tKQX
Q2
ADSP is blocked by E
E1 masks ADSP
A
Suspend Burst
Q2
B
GS82032AT/Q-180/166/133/100
Q2
ADSC initiated read
1
inactive
C
RD3
© 2000, Giga Semiconductor, Inc.
Q2
Deselected with E
tH
tH
D
tKQX
Q3
A
tHZ
2

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