SAA5290ZP Philips Semiconductors, SAA5290ZP Datasheet - Page 23

• Manufacturer Part Number: SAA5290ZP
• Description: One page Economy Teletext/TV microcontroller
• Manufacturer: Philips Semiconductors

Philips Semiconductors
TELETEXT DECODER FUNCTIONAL DESCRIPTION
Data slicer
The data slicer extracts the digital teletext data from the
incoming analog waveform. This is performed by sampling
the CVBS waveform and processing the samples to
extract the teletext data and clock.
Acquisition timing
The acquisition timing is generated from a logic level
positive-going composite sync signal ‘VCS’. This signal is
generated by the sync separator circuit which adaptively
slices the sync pulses at 50% of their height. It is able to do
this over a wide range of sync amplitudes by using the
same basic principle used on VIP1 (SAA5230) and VIP2
(SAA5231).
Figure 4 is a block diagram showing the principles of
operation. It relies upon the fact that the ratio of the sync
width to the line time is approximately 13 : 1. In order to
slice the sync pulse at the correct 50% level two currents
are generated.
February 1995
handbook, full pagewidth
One page Economy Teletext/TV
microcontroller
CVBS
V DD
Fig.4 Sync separator block diagram.
1/39V (mA)
1/3V (mA)
(= slicing level)
i
FILTER
i
V ref
23
gated negative peak detector
One is constant and is proportional to the difference
between the black level of the video and the slicing level.
The other is produced only when the video is below the
slicing level, and is also proportional to the difference
between the slicing level and the input, but has a
magnitude13 times greater.
The black level is determined by a sync-gated peak
detector. The video is negatively peak detected into an
external capacitor (BLACK, pin 25), but not during the
sync pulse VCS. The two currents are integrated on the
CVBS input coupling capacitor and the net effect is to alter
the mean input voltage until the (fixed) slicing level is
correct.
The acquisition clocking and timing are locked to the VCS
signal using a digital phased-locked-loop. The phase error
in the acquisition phase-locked-loop is detected by a
signal quality circuit which disables acquisition if poor
signal quality is detected.
V ref
V ref
FILTER
BLACK
MLC105
VCS
Preliminary specification
SAA5290