SAA5531 Philips Semiconductors, SAA5531 Datasheet - Page 10

• Manufacturer Part Number: SAA5531
• Description: Enhanced TV microcontrollers with On-Screen Display OSD
• Manufacturer: Philips Semiconductors

Philips Semiconductors
7
The functionality of the microcontroller used on this device
is described here with reference to the industry standard
80C51 microcontroller. A full description of its functionality
can be found in “Handbook IC20, 80C51-Based 8-bit
Microcontrollers”.
7.1
8
The device has the capability of a maximum of 128-kbyte
Program ROM and 12-kbyte Data RAM internally.
8.1
The 64-kbyte device has a continuous address space from
0 to 64 kbytes. The 128-kbyte memory is arranged in four
banks of 32 kbytes. One of the 32-kbyte banks is common
and is always addressable. The other three banks
(Bank 0, Bank 1 and Bank 2) can be accessed by
selecting the right bank via the SFR ROMBK bits; see
Table 2.
The ROM bank switching is handled and supported by the
compiler and linker development tools.
2000 Feb 23
80C51 microcontroller core standard instruction set and
timing
1 s machine cycle
Maximum 128K
Maximum of 12K
Interrupt Controller for individual enable/disable with two
level priority
Two 16-bit Timer/Counter registers
Watchdog Timer
Auxiliary RAM page pointer
16-bit Data pointer
Idle and Power-down mode
29 general I/O lines
Eight 6-bit Pulse Width Modulator (PWM) outputs for
control of TV analog signals
One 14-bit PWM for Voltage Synthesis Tuner (VST)
control
8-bit ADC with 4 multiplexed inputs
2 high current outputs for directly driving LEDs etc.
I
Enhanced TV microcontrollers with
On-Screen Display (OSD)
2
C byte level bus interface with dual ports.
MICROCONTROLLER
MEMORY ORGANIZATION
Microcontroller features
ROM bank switching
8-bit Program ROM
8-bit Auxiliary RAM
10
Table 2 ROM bank selection
8.2
SAA55xx devices have a set of security bits allied with
each section of the device, i.e. Program ROM, Character
ROM and Packet 26 ROM. The security bits are used to
prevent the ROM from being overwritten once
programmed, and also the contents being verified once
programmed. The security bits are one-time
programmable and cannot be erased.
The SAA55xx memory and security bits are structured as
shown in Fig.5. The SAA55xx security bits are set as
shown in Fig.6 for production programmed devices and
are set as shown in Fig.7 for production blank devices.
8.3
The internal Data RAM is organised into two areas, Data
memory and Special Function Registers (SFRs) as shown
in Fig.8.
8.4
The Data memory is 256
address range 00H to FFH when using indirect addressing
and 00H to 7FH when using direct addressing. The SFRs
occupy the address range 80H to FFH and are accessible
using direct addressing only.
The lower 128 bytes of Data memory are mapped as
shown in Fig.9. The lowest 24 bytes are grouped into
4 banks of 8 registers, the next 16 bytes above the register
banks form a block of bit addressable memory space.
The upper 128 bytes is not allocated for any special area
or functions.
Table 3 Bank selection
ROMBK1 ROMBK0 0 TO 32-kbyte 32 TO 64-kbyte
0
0
1
1
Security bits - program and verify
RAM organisation
Data memory
RS1
0
0
1
1
0
1
0
1
RS0
reserved
common
common
common
8 bits and occupies the
0
1
0
1
Preliminary specification
SAA55xx
reserved
Bank 0
Bank 1
Bank 2
Bank 3
BANK
Bank 0
Bank 1
Bank 2