CDP1871 Intersil Corporation, CDP1871 Datasheet - Page 8

• Manufacturer Part Number: CDP1871
• Description: CMOS Keyboard Encoder
• Manufacturer: Intersil Corporation

and read by the CPU, at which time the next key pressed in
the scanning order is detected. If the first key remains closed
after the CPU reads the data and resets the DA output, on
the low-to-high transition of TPB, an auxiliary signal (RPT) is
generated and is available to the CPU to indicate an auto-
repeat condition. The RPT output is reset high at the end of
the debounce delay after the depressed key is released.
The DEBOUNCE input provides a terminal connection for an
external user-selected RC circuit to eliminate false detection
of a keydown condition caused by keyboard noise. The oper-
ation of the DEBOUNCE circuit is shown in Figure 2 (Pin
36). When a valid keydown is detected, the on-chip active-
resistor device (R
Dynamic Electrical Specifications
NOTES:
Clock Cycle Time
Clock Pulse Width High
Data Available Valid Delay
Data Available Invalid Delay
Scan Count Delay
(Non-Repeat)
Data Out Valid Delay
Data Out Hold Time
Repeat Valid Delay
Repeat Invalid Delay
1. Typical values are for T
2. t
t
k = 0.9ns per pF
c = Keyboard capacitance (pF)
CC
CWL
= t
= t
CWH
CD1
PARAMETER
+ t
+ KC
CWL
N
) is enabled and the external capacitor
A
= +25
t
o
t
t
t
t
t
t
t
CWH
t
DAH
CDH
RPH
DAL
CD1
CDV
RPL
C and nominal V
CC
V
(V)
10
10
10
10
10
10
10
10
10
5
5
5
5
5
5
5
5
5
DD
At T
CDP1871A, CDP1871AC
A
DD
= -40 to +85
MIN
100
.
50
CDP1871AD, CDP1871AE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
o
(NOTE 1)
C, V
4-73
TYP
260
130
850
425
120
100
150
350
170
40
20
70
35
60
50
75
-
-
DD
(C
R
inverter, which clocks the DA flip-flop (latching the DA output
low and inhibiting the scan clock). (The DA F/F is reset by
the low-to-high transition of TPB when the CS inputs are
enabled). When a valid key-release is detected RN is dis-
abled and C
(R
charge time is again sensed by the Schmitt-trigger inverter,
enabling the scan clock to continue on the next high-to-low
transitions of TPB, after the current keycode data is read by
the CPU.
N
X
X
C
5%, Unless Otherwise Specified
) is discharged, providing a key closure debounce time
), providing a key-release debounce time
X
. This discharge is sensed by the Schmitt-trigger
MAX
1900
500
250
150
950
250
125
200
100
400
200
700
350
75
-
-
-
-
LIMITS
X
begins to charge through the external resistor
CDP1871ACD, CDP1871ACE
MIN
100
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(NOTE 1)
TYP
260
850
120
100
150
350
40
70
-
-
-
-
-
-
-
-
-
-
MAX
1900
500
150
250
200
400
700
-
-
-
-
-
-
-
-
-
-
-
R
X
UNITS
Note 2
Note 2
C
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
X
. This