M366S1723ETS-C7A Samsung semiconductor, M366S1723ETS-C7A Datasheet - Page 13

• Manufacturer Part Number: M366S1723ETS-C7A
• Description: (M3xxSxxxxETx-C7A) SDRAM Unbuffered Module
• Manufacturer: Samsung semiconductor

M366S3323ETS(U) (32M x 64, 256MB Module)
(Recommended operating condition unless otherwise noted, T
(Recommended operating condition unless otherwise noted, T
DC CHARACTERISTICS
M374S1723ETS(U) (16M x 72, 128MB Module)
Notes : 1. Measured with outputs open.
64MB, 128MB, 256MB Unbuffered DIMM
Operating current
(One bank active)
Precharge standby current
in power-down mode
Precharge standby current
in non power-down mode
Active standby current in
power-down mode
Active standby current in
non power-down mode
(One bank active)
Operating current
(Burst mode)
Refresh current
Self refresh current
Operating current
(One bank active)
Precharge standby current
in power-down mode
Precharge standby current
in non power-down mode
Active standby current in
power-down mode
Active standby current in
non power-down mode
(One bank active)
Operating current
(Burst mode)
Refresh current
Self refresh current
2. Refresh period is 64ms.
Parameter
Parameter
Symbol
Symbol
I
I
I
I
I
I
I
I
CC2
CC3
CC2
CC3
CC2
I
CC3
I
CC2
I
CC3
I
I
I
I
I
CC2
CC3
CC2
CC3
CC2
CC2
CC3
CC3
I
I
I
I
I
I
I
I
CC1
CC4
CC5
CC6
CC1
CC4
CC5
CC6
NS
NS
NS
NS
PS
PS
PS
PS
N
N
N
N
P
P
P
P
Burst length = 1
t
I
CKE ≤ V
CKE & CLK ≤ V
CKE ≥ V
Input signals are changed one time during 20ns
CKE ≥ V
Input signals are stable
CKE ≤ V
CKE & CLK ≤ V
CKE ≥ V
Input signals are changed one time during 20ns
CKE ≥ V
Input signals are stable
I
Page burst
4Banks activated
t
t
CKE ≤ 0.2V
Burst length = 1
t
I
CKE ≤ V
CKE & CLK ≤ V
CKE ≥ V
Input signals are changed one time during 20ns
CKE ≥ V
Input signals are stable
CKE ≤ V
CKE & CLK ≤ V
CKE ≥ V
Input signals are changed one time during 20ns
CKE ≥ V
Input signals are stable
I
Page burst
4Banks activated
t
t
CKE ≤ 0.2V
RC
O
O
CCD
RC
RC
O
O
CCD
RC
= 0 mA
= 0 mA
= 0 mA
= 0 mA
≥ t
≥ t
≥ t
≥ t
= 2CLKs
= 2CLKs
RC
RC
RC
RC
(min)
IL
IH
IH
IL
IH
IH
(min)
(min)
IL
IH
IH
IL
IH
IH
(min)
(max), t
(max), t
(max), t
(max), t
(min), CS ≥ V
(min), CLK ≤ V
(min), CS ≥ V
(min), CLK ≤ V
(min), CS ≥ V
(min), CLK ≤ V
(min), CS ≥ V
(min), CLK ≤ V
IL
IL
IL
IL
A
A
Test Condition
Test Condition
(max), t
(max), t
(max), t
(max), t
= 0 to 70°C)
CC
CC
= 0 to 70°C)
CC
CC
= 10ns
= 10ns
= 10ns
= 10ns
IH
IH
IH
IH
CC
CC
CC
CC
IL
IL
IL
IL
(min), t
(min), t
(min), t
(min), t
(max), t
(max), t
(max), t
(max), t
=∞
=∞
=∞
=∞
CC
CC
CC
CC
CC
CC
CC
CC
= 10ns
= 10ns
= 10ns
= 10ns
=∞
=∞
=∞
=∞
C
C
Rev. 1.3 February 2004
Version
Version
1120
1840
1800
960
320
160
480
400
810
180
270
225
990
-7A
-7A
32
32
80
80
32
18
18
90
45
45
18
Unit
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
SDRAM
Note
Note
1
1
2
1
1
2