PSD913F1-B-90JI ST Microelectronics, PSD913F1-B-90JI Datasheet - Page 64

• Manufacturer Part Number: PSD913F1-B-90JI
• Description: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
• Manufacturer: ST Microelectronics

The
PSD9XX
Functional
Blocks
(cont.)
60
PSD9XX Family
Table 33. Status During Power On Reset, Warm Reset and Power Down Mode
9.5.3.4 Reset of Flash Erase and Programming Cycles (PSD934F2 and PSD954F2)
An external reset on the RESET pin will also reset the internal Flash memory state
machine. When the Flash is in programming or erase mode, the RESET pin will terminate
the programming or erase operation and return the Flash back to read mode in tNLNH-A
(minimum 25 µs) time.
9.6 Programming In-Circuit using the JTAG Interface
The JTAG interface on the PSD9XX can be enabled on Port C (see Table 34). All
memory (Flash and Secondary Flash Block), PLD logic, and PSD configuration bits may be
programmed through the JTAG interface. A blank part can be mounted on a printed circuit
board and programmed using JTAG.
The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional
signals, TSTAT and TERR, are optional JTAG extensions used to speed up program and
erase operations.
See Application Note 54 for more details on JTAG In-System-Programming.
*
**
Table 34. JTAG Port Signals
Port Configuration
SR_cod bit in the VM Register are always cleared to zero on power on or warm reset.
By default, on a blank PSD (as shipped from factory or after erasure), four pins on Port C
are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO.
PMMR0, 2
VM Register*
All other registers
Port C Pin
MCU I/O
PLD Output
Address Out
Data Port
Register
PC0
PC1
PC3
PC4
PC5
PC6
JTAG Signals
TSTAT
Input Mode
Valid after internal
PSD configuration
bits are loaded
Tri-stated
Tri-stated
Cleared to “0”
Initialized based on
the selection in
PSDsoft
Configuration Menu.
Cleared to “0”
TERR
TMS
TDO
TCK
TDI
Power On Reset
Power On Reset
Mode Select
Clock
Status
Error Flag
Serial Data In
Serial Data Out
Description
Unchanged
Initialized based on
the selection in
PSDsoft
Configuration Menu.
Cleared to “0”
Warm Reset
Warm Reset
Input Mode
Valid
Tri-stated
Tri-stated
Unchanged
Depend on inputs to
PLD (address are
blocked in PD mode)
Not defined
Tri-stated
Unchanged
Preliminary Information
Power Down Mode
Power Down Mode
Unchanged
Unchanged