QL4009 QuickLogic, QL4009 Datasheet

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QL4009

Manufacturer Part Number
QL4009
Description
Quick RAM
Manufacturer
QuickLogic
Datasheet

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QL4009 Rev B
QL4009 - QuickRAM
Device Highlights
High Performance & High Density
High Speed Embedded SRAM
Easy to Use / Fast Development Cycles
Advanced I/O Capabilities
160+ MHz FIFOs
smallest die sizes
9,000 Usable PLD Gates with 82 I/Os
300 MHz 16-bit Counters, 400 MHz Datapaths,
0.35µm four-layer metal non-volatile CMOS process for
8 dual-port RAM modules, organized in user-configurable
1,152 bit blocks
5ns access times, each port independently accessible
Fast and effecient for FIFO, RAM, and ROM functions
100% routable with 100% utilization and complete
pin-out stability
Variable-grain logic cells provide high performance and
100% utilization
Comprehensive design tools include high quality
Verilog/VHDL synthesis
Interfaces with both 3.3 volt and 5.0 bolt devices
PCI compliant with 3.3V and 5.0V busses for -1/-2/-3/-4
speed grades
Full JTAG boundary scan
Registered I/O cells with individually controlled clocks and
output enables
9,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density, and Embedded RAM
D
EVICE
H
IGHLIGHTS
QL4009 - QuickRAM
The QuickRAM family of ESPs (Embedded Standard
Products) offers FPGA logic in combination with Dual-
Port SRAM modules. The QL4009 is a 9,000 usable
PLD gate member of the QuickRAM family of ESPs.
QuickRAM ESPs are fabricated on a 0.35mm four-
layer metal process using QuickLogic’s patented
ViaLink
tion of high performance, high density, low cost, and
extreme ease-of-use.
The QL4009 contains 160 logic cells and 8 dual port
RAM modules (see Figure 1). Each RAM module has
1,152 RAM bits, for a total of 9,216 bits. RAM Mod-
ules are Dual Port (one read port, one write port) and
can be configured into one of four modes: 64 (deep)
x18 (wide), 128x9, 256x4, or 512x2 (see Figure 2).
With a maximum of 82 I/Os, the QL4009 is available
in 68-pin PLCC, 84-pin PLCC, and 100-pin TQFP
packages.
Designers can cascade multiple RAM modules to
increase the depth or width allowed in single modules
by connecting corresponding address lines together
and dividing the words between modules (see Figure
3). This approach allows up to 512-deep configura-
tions as large as 16 bits wide in the smallest Quick-
RAM device and 44 bits wide in the largest device.
A
FIGURE 1. QuickRAM Block Diagram
TM
8 RAM
Blocks
RCHITECTURE
technology to provide a unique combina-
TM
O
VERVIEW
}
High Speed
Logic Cells
Interface
160
6-11

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QL4009 Summary of contents

Page 1

... TM tion of high performance, high density, low cost, and extreme ease-of-use. The QL4009 contains 160 logic cells and 8 dual port RAM modules (see Figure 1). Each RAM module has 1,152 RAM bits, for a total of 9,216 bits. RAM Mod- ules are Dual Port (one read port, one write port) and can be configured into one of four modes: 64 (deep) x18 (wide), 128x9, 256x4, or 512x2 (see Figure 2) ...

Page 2

... FIGURE 2. QuickRAM Module Software support for the complete QuickRAM fam- ily, including the QL4009, is available through two basic packages. The turnkey QuickWorksTM pack- age provides the most complete ESP software solu- tion from design entry to logic synthesis, to place and route, to simulation. The QuickTools ...

Page 3

... QL4009 - QuickRAM 68 Pin PLCC Pinout Diagram 84 Pin PLCC Pinout Diagram TM 6-13 ...

Page 4

... QL4009 - QuickRAM PIN # 1 PIN # 26 100 Function TQFP ACLK / GCLK / 6-14 14 QuickRAM QL4009-1PF100C 100-Pin TQFP 100 100 100 Function Function TQFP TQFP TQFP I/O 26 TDI 51 I/O 76 I/O 27 I/O 52 I/O 77 I/O 28 I/O 53 I/O 78 I/O 29 I/O 54 ...

Page 5

... QL4009 - QuickRAM ESCRIPTIONS Pin Function TDI/RSI Test Data In for JTAG / RAM init. Serial Data In TRSTB/RRO Active low Reset for JTAG / RAM init. reset out TMS Test Mode Select for JTAG TCK Test Clock for JTAG TDO/RCO Test data out for JTAG / RAM init ...

Page 6

... QL4009 - QuickRAM VCC Voltage..................................-0.5 to 4.6V VCCIO Voltage ..............................-0.5 to 7.0V Input Voltage..................... -0.5 to VCCIO+0.5V Latch-up Immunity ..............................±200mA Symbol Parameter VCC Supply Voltage VCCIO I/O Input Tolerance Voltage TA Ambient Temperature TC Case Temperature -0 Speed Grade K Delay Factor -1 Speed Grade -2 Speed Grade -3 Speed Grade -4 Speed Grade Symbol Parameter VIH Input HIGH Voltage ...

Page 7

... QL4009 - QuickRAM AC CHARACTERISTICS at VCC = 3.3V 25° 1.00) (To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.) Symbol Parameter tPD Combinatorial Delay [6] tSU Setup Time [6] tH Hold Time tCLK Clock to Q Delay tCWHI Clock High Time tCWLO Clock Low Time ...

Page 8

... QL4009 - QuickRAM RAM Cell Synchronous Read Timing Symbol Parameter TSRA RA Setup Time to RCLK THRA RA Hold Time to RCLK TSRE RE Setup Time to RCLK THRE RE Hold Time to RCLK TRCRD RCLK to RD [5] RAM Cell Asynchronous Read Timing Symbol Parameter RPDRD [5] Symbol TIN High Drive Input Delay ...

Page 9

... QL4009 - QuickRAM Symbol Parameter tI/O Input Delay (bidirectional pad) TISU Input Register Set-Up Time TIH Input Register Hold Time TlOCLK Input Register Clock To Q TlORST Input Register Reset Delay TlESU Input Register clock Enable Set-Up Time TlEH Input Register Clock Enable Hold Time ...

Page 10

... QL4009 - QuickRAM 6- Preliminary ...

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