K7R321882 Samsung semiconductor, K7R321882 Datasheet - Page 6

• Manufacturer Part Number: K7R321882
• Description: 1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
• Manufacturer: Samsung semiconductor

K7R323682M
K7R321882M
K7R320982M
GENERAL DESCRIPTION
Read Operations
The K7R323682M,K7R321882M and K7R320982M are 37,748,736-bits QDR(Quad Data Rate)
Synchronous Pipelined Burst SRAMs.
They are organized as 1,048,576 words by 36bits for K7R323682M, 2,097,152 words by 18 bits for K7R321882M and 4,194,304
words by 9bits for K7R320982M.
The QDR operation is possible by supporting DDR read and write operations through separate data output and input ports
And totally independent read and write ports eliminate the need for high speed bus turn around.
Address, data inputs, and all control signals are synchronized to the input clock ( K or K ).
Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,
Read data are referenced to echo clock ( CQ or CQ ) outputs.
Read address is registered on rising edges of the input K clocks, and write address is
Common address bus is used to access address both for read and write operations.
The internal burst counter is fiexd to 2-bit sequential for both read and write operations.
Synchronous pipeline read and early write enable high speed operations.
Simple depth expansion is accomplished by using R and W for port selection.
Byte write operation is supported with BW
Nybble write operation is supported with NW
IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system.
The K7R323682M,K7R321882M and K7R320982M are implemented with SAMSUNG's high performance
6T CMOS technology and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.
Read cycles are initiated by activating R at the rising edge of the positive input clock K.
Address is presented and stored in the read address register synchronized with K clock.
For 2-bit burst DDR operation, it will access two 36-bit or 18-bit or 9-bit or 8-bit data words with each read command.
The first pipelined data is transfered out of the device triggered by C clock following next K clock rising edge.
Next burst data is triggered by the rising edge of following C clock rising edge.
Continuous read operations are initated with K clock rising edge.
And pipelined data are transferred out of device on every rising edge of both C and C clocks.
In case C and C tied to high, output data are triggered by K and K insted of C and C.
When the R is disabled after a read operation, the K7R323682M,K7R321882M and K7R320982M will first complete
burst read operation before entering into deselect mode at the next K clock rising edge.
Then output drivers disabled automatically to high impedance state.
Power-Up/Power-Down Supply Voltage Sequencing
with the same cycle. Memory bandwidth is maxmized as data can be transfered into sram
on every rising edge of K and K , and transfered out of sram on every rising edge of C and C.
the data outputs are synchronized to the input clocks ( K and K ).
registered on rising edges of the input K clocks.
The following power-up supply voltage application is recommended: V
simultaneously, as long as V
removal sequence is recommended: V
does not exceed V
DD
by more than 0.5V during power-down.
DDQ
does not exceed V
IN
, V
0
and BW
0
REF
and NW
, V
DDQ
1
DD
1Mx36 & 2Mx18 & 4Mx9 QDR
( BW
1
, V
by more than 0.5V during power-up. The following power-down supply voltage
pins for x8 device.
DD
2
and B W
, V
SS
- 6 -
. V
3)
DD
pins for x18 ( x36 ) device and only BW pin for x9 device.
SS
and V
, V
DD
DDQ
, V
DDQ
can be removed simultaneously, as long as V
, V
REF
, then V
I N
. V
DD
TM
and V
II b2 SRAM
DDQ
can be applied
Dec. 2003
Rev 2.0
DDQ