CX28398 Conexant Systems, CX28398 Datasheet - Page 12
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CX28398
Manufacturer Part Number
CX28398
Description
(CX28394 - CX28398) Quad/x16/Octal?T1/E1/J1 Framers
Manufacturer
Conexant Systems
Datasheet
1.CX28398.pdf
(305 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CX28398-23
Manufacturer:
MINDSPEED
Quantity:
263
Company:
Part Number:
CX28398G-26
Manufacturer:
PEREGRIN
Quantity:
2 000
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Table of Contents
3.15 Data Link Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-75
3.16 System Bus Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-94
0A4—DL1 Time Slot Enable (DL1_TS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-75
0A5—DL1 Bit Enable (DL1_BIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76
0A6—DL1 Control (DL1_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76
0A7—RDL #1 FIFO Fill Control (RDL1_FFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77
0A8—Receive Data Link FIFO #1 (RDL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-79
0A9—RDL #1 Status (RDL1_STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-80
0AA—Performance Report Message (PRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-81
0AB—TDL #1 FIFO Empty Control (TDL1_FEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-82
0AC—TDL #1 End Of Message Control (TDL1_EOM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83
0AD—Transmit Data Link FIFO #1 (TDL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83
0AE—TDL #1 Status (TDL1_STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83
0AF—DL2 Time Slot Enable (DL2_TS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-84
0B0—DL2 Bit Enable (DL2_BIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-85
0B1—DL2 Control (DL2_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-85
0B2—RDL #2 FIFO Fill Control (RDL2_FFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-87
0B3—Receive Data Link FIFO #2 (RDL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-88
0B4—RDL #2 Status (RDL2_STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-89
0B6—TDL #2 FIFO Empty Control (TDL2_FEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-90
0B7—TDL #2 End Of Message Control (TDL2_EOM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-90
0B8—Transmit Data Link FIFO #2 (TDL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-91
0B9—TDL #2 Status (TDL2_STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-91
0BA—DLINK Test Configuration (DL_TEST1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-92
0BB—DLINK Test Status (DL_TEST2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-92
0BC—DLINK Test Status (DL_TEST3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-92
0BD—DLINK Test Control #1 or Configuration #2 (DL_TEST4) . . . . . . . . . . . . . . . . . . . 3-92
0BE—DLINK Test Control #2 or Configuration #2 (DL_TEST5) . . . . . . . . . . . . . . . . . . . . 3-93
0D0—System Bus Interface Configuration (SBI_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-94
0D1—Receive System Bus Configuration (RSB_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-96
0D2—RSB Sync Bit Offset (RSYNC_BIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-97
0D3—RSB Sync Time Slot Offset (RSYNC_TS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-98
0D4—Transmit System Bus Configuration (TSB_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-99
0D5—TSB Sync Bit Offset (TSYNC_BIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-100
0D6—TSB Sync Time Slot Offset (TSYNC_TS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-101
0D7—Receive Signaling Configuration (RSIG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-102
0D8—Signaling Reinsertion Frame Offset (RSYNC_FRM) . . . . . . . . . . . . . . . . . . . . . . 3-104
0D9—Slip Buffer Status (SSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-105
0DA—Receive Signaling Stack (STACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-107
0DB—RSLIP Phase Status (RPHASE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-108
0DC—TSLIP Phase Status (TPHASE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-108
0DD—RAM Parity Status (PERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-109
0E0–0FF—System Bus Per-Channel Control (SBCn; n = 0 to 31) . . . . . . . . . . . . . . . . . 3-109
100–11F—Transmit Per-Channel Control (TPCn; n = 0 to 31) . . . . . . . . . . . . . . . . . . . 3-110
120–13F—Transmit Signaling Buffer (TSIGn; n = 0 to 31) . . . . . . . . . . . . . . . . . . . . . . 3-112
Conexant
Quad/x16/Octal—T1/E1/J1 Framers
CX28394/28395/28398
100054E
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