AS7C252MPFD18A-133TQC ALSC [Alliance Semiconductor Corporation], AS7C252MPFD18A-133TQC Datasheet
AS7C252MPFD18A-133TQC
Related parts for AS7C252MPFD18A-133TQC
AS7C252MPFD18A-133TQC Summary of contents
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... Q DQa Byte Write registers CLK D Q Enable register CE CLK D Q Enable Power delay down register CLK -200 5 200 3.1 450 170 90 Alliance Semiconductor AS7C252MPFD18A Memory 21 array Input Output registers registers CLK CLK 18 DQ[a,b] -166 -133 6 7.5 166 133 3.5 3.8 400 350 150 ...
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... Mode PL-SCD PL-SCD PL-SCD PL-DCD PL-DCD PL-DCD NTD-PL NTD-PL NTD-PL NTD-FT NTD-FT NTD- Alliance Semiconductor AS7C252MPFD18A Speed 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/10 ns 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/ ...
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... V 20 DDQ V 21 SSQ DQb6 22 DQb7 23 24 DQPb SSQ V 27 DDQ 2/11/05, v.1.1 ® TQFP 14 x 20mm Alliance Semiconductor AS7C252MPFD18A DDQ 76 V SSQ 75 NC DQPa 74 73 DQa7 72 DQa6 71 V SSQ 70 V DDQ 69 DQa5 68 DQa4 ...
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... Functional description The AS7C252MPFD18A is a high-performance CMOS 32-Mbit synchronous Static Random Access Memory (SRAM) device organized as 2,097,152 words × 18 bits. It incorporates a two-stage register-register pipeline for highest frequency on any given technology. Fast cycle times of 5/6/7.5 ns with clock access times (t Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP) ...
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... DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE. PUS 2/11/05, v.1.1 ® or left floating, device follows interleaved Burst order. When DD is guaranteed after the time t is met. After entering SNOOZE MODE, all inputs except ZZ is SB2 ZZI Alliance Semiconductor AS7C252MPFD18A Description . The duration of SB2 ...
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... High Starting Address First Increment Second Increment Third Increment Alliance Semiconductor AS7C252MPFD18A Linear burst address (LBO = ...
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... External Alliance Semiconductor AS7C252MPFD18A CLK Operation Deselect Deselect Deselect Deselect Deselect Begin read Begin read Begin read ...
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... < Max Deselected < 0.2V, I SB1 ≤ 0.2V or ≥ V all ≥ V Deselected Max I SB2 ≤ ≥ V all Alliance Semiconductor AS7C252MPFD18A Min Max –0.3 +3.6 –0 0.3 DD –0 0.3 DDQ – 1.8 – 20 –65 +150 –65 +135 Min Nominal Max 2 ...
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... ADSCS t 0.4 – 0.5 ADVH t 0.4 – 0.5 ADSPH t 0.4 – 0.5 ADSCH Conditions Symbol ZZ > SB2 t PDS t PUS t ZZI t RZZI Alliance Semiconductor AS7C252MPFD18A -133 Max Min Max Unit Notes 166 – 133 MHz – 7.5 – ns 3.5 – 3.8 ns 3.5 – 3.8 ns – 0 – ns 2,3,4 – 1.5 – – 0 – ...
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... ADV inserts wait states HZOE t OH Q(A2) Q(A2Ý01) Q(A2Ý10) Read Burst Burst Suspend Burst Q(A2) Read Read Read Read Q(A 2Ý01 ) Q(A 2Ý10 ) Q(A 2Ý10 ) Q(A 2Ý11 ) Alliance Semiconductor AS7C252MPFD18A Undefined A3 t HZC Q(A2Ý11) Q(A3) Q(A3Ý01) Q(A3Ý10) Read Burst Burst Burst Q(A3) Read Read Read DSEL* Q(A 3Ý01 ) Q(A 3Ý10 ) Q(A 3Ý ...
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... CL ADSC LOADS NEW ADDRESS A2 ADV SUSPENDS BURST D(A2) D(A2Ý01) D(A2Ý01) D(A2Ý10) ADV Suspend Read Suspend Burst Write Q(A2) Write Write D D(A 2Ý01 ) D(A 2Ý01 ) D(A 2Ý10 ) Alliance Semiconductor AS7C252MPFD18A t t ADSCS ADSCH ADVH ADVS D(A2Ý11) D(A3) D(A3Ý01) D(A3Ý10) ADV ADV ...
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... ADVH ADVS D(A2 HZOE LZOE t LZC Q(A1) Suspend Read Suspend Read Read Q(A2) Write Q(A3) Q(A1) D Alliance Semiconductor AS7C252MPFD18A Q(A3) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11) ADV ADV ADV Burst Burst Burst Read Read Read Q(A 3Ý01 ) Q(A 3Ý10 ) Q(A 3Ý ...
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... GWE t t CSS CSH CE0,CE2 CE1 ADV LZOE Q(A1) Dout Din READ READ Q(A1) Q(A2) 2/11/05, v.1.1 ® t CYC HZOE Q(A2) Q(A3) Q(A4 D(A5) D(A6) READ READ WRITE Q(A3) Q(A4) D(A5) Alliance Semiconductor AS7C252MPFD18A LZOE Q(A8 D(A7) READ WRITE WRITE READ Q(A9) D(A7) D(A6) Q(A8 Q(A9 ...
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... Dout Q(A1 supply S READ USPEND READ Q(A1) Q(A1) 2/11/05, v.1.1 ® HZC t PUS t PDS ZZ Recovery Cycle ZZ Setup Cycle t ZZI t RZZI I SB2 Sleep State Alliance Semiconductor AS7C252MPFD18A t CYC D(A2) t HZOE D(A2(Ý01)) Normal Operation Mode READ USPEND Q(A2) WRITE TINUE D(A2) WRITE D( Ý01) ...
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... DDQ OUT 30 pF* Figure B: Output load (A) at any given temperature and voltage. LZC is measured as low if below VIL. CL Alliance Semiconductor AS7C252MPFD18A Thevenin equivalent: +2.5V 319Ω/1667Ω D OUT /2 5 pF* 353Ω/1538Ω GND *including scope and jig capacitance Figure C: Output load(B) ...
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... Package dimensions 100-pin quad flat pack (TQFP) TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e 0.65 nominal Hd 15.85 16.15 He 21.80 22.20 L 0.45 0.75 L1 1.00 nominal α 0° 7° Dimensions in millimeters 2/11/05, v.1.1 ® Alliance Semiconductor AS7C252MPFD18A α ...
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... Production version first production version 8. Clock speed (MHz) 9. Package type TQFP 10. Operating temperature commercial (0° 70° C industrial (-40° 85° Lead Free Part 2/11/05, v.1.1 ® -166 AS7C252MPFD18A-166TQC AS7C252MPFD18A-166TQI Alliance Semiconductor AS7C252MPFD18A -133 AS7C252MPFD18A-133TQC AS7C252MPFD18A-133TQI N) –XXX TQ C ...
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... Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. AS7C252MPFD18A ® Copyright © Alliance Semiconductor All Rights Reserved Part Number: AS7C252MPFD18A Document Version: v.1.1 ...