AS7C252MPFD18A-133TQC ALSC [Alliance Semiconductor Corporation], AS7C252MPFD18A-133TQC Datasheet - Page 6

• Manufacturer Part Number: AS7C252MPFD18A-133TQC
• Description: 2.5V 2M x 18 pipelined burst synchronous SRAM
• Manufacturer: ALSC [Alliance Semiconductor Corporation]

Write enable truth table (per byte)
Key: X = don’t care, L = low, H = high, n = a, b;
Asynchronous Truth Table
Notes:
1. X means “Don’t Care”
2. ZZ pin is pulled down internally
3. For write cycles that follows read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur.
4. Snooze mode means power down state of which stand-by current does not depend on cycle times
5. Deselected means power down state of which stand-by current depends on cycle times
Burst sequence table
Write All Bytes
Write Byte a
Write Byte b
Read
Snooze mode
Read
Write
Deselected
Starting Address
First Increment
Second Increment
Third Increment
2/11/05,
Operation
Function
v.1.1
Interleaved burst address (LBO = 1)
A1 A0
ZZ
GWE
0 0
0 1
1 0
1 1
H
L
L
L
L
H
H
H
H
H
L
A1 A0
BWE
0 1
0 0
1 1
1 0
X
H
L
L
L
L
OE
X
H
X
X
L
BWE
,
BWa
Alliance Semiconductor
A1 A0
BWn
1 0
1 1
0 0
0 1
X
H
X
H
L
L
Din, High-Z
I/O Status
High-Z
High-Z
High-Z
= internal write signal.
Dout
BWb
A1 A0
X
H
X
H
L
L
1 1
1 0
0 1
0 0
Starting Address
First Increment
Second Increment
Third Increment
®
Linear burst address (LBO = 0)
A1 A0
0 0
0 1
1 0
1 1
AS7C252MPFD18A
A1 A0
0 1
1 0
1 1
1 0
A1 A0
1 0
1 1
0 0
0 1
6 of 18
A1 A0
1 1
0 0
0 1
1 0