GS815018AB GSI [GSI Technology], GS815018AB Datasheet
GS815018AB
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GS815018AB Summary of contents
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BGA Commercial Temp 18Mb Register-Register Late Write SRAM Industrial Temp Features • Register-Register Late Write mode, Pipelined Read mode • 2.5 V +200/–200 mV core power supply • 1 1.8 V HSTL Interface • ZQ controlled programmable ...
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GS815036 Pinout—119-Bump BGA—Top View (Package Rev: 1.05 10/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 1 ...
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GS815018 Pinout—119-Bump BGA—Top View (Package Rev: 1.05 10/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 1 ...
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GS815018/36 BGA Pin Description Symbol Type I — ...
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Write Operations Write operations are initiated when the write enable input signal (SW) and chip select (SS) are captured at logic rising edge of the K clock (and falling edge of the K clock). Late Write In ...
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Register-Register Late Write, Pipelined Read Truth Table ↑ ↑ ↑ ↑ ...
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Absolute Maximum Ratings (All voltages reference Symbol V Voltage Voltage in V DDQ V I/O V Voltage on Other Input Pins IN I Input Current on Any Pin IN I Output Current ...
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Undershoot Measurement and Timing 50% V – 1 20% tKC Rev: 1.05 10/2005 ...
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Capacitance 1 Parameter Input Capacitance Output Capacitance Output Capacitance (Clock) Note: This parameter is sample tested. AC Test Conditions Parameter Input high level Input ...
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Input and Output Leakage Characteristics Parameter Input Leakage Current (except mode pins) ZQ, MCH, MCL, EP2, EP3 Pin Input Current Output Leakage Current Operating Currents Parameter Symbol I x36 650 mA DD Operating Current I x18 600 mA DD HSTL ...
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AC Electrical Characteristics Parameter Clock Cycle Time Clock High Time Clock Low Time Clock High to Output Low-Z Clock High to Output Valid Clock High to Output Invalid Clock High to Output High-Z Address Valid to Clock High Clock High ...
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G Controlled Read-Write Read A1 Read A2 KHKL KHKL KHKH KHKH KLKH KLKH K tAVKH tKHAX tWVKH tKHWX SW BWx GLQV DQn Note not shown; assumes K tied to V REF Read A1 Read ...
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Read A1 Read A2 KHKL KHKL KHKH KHKH KLKH KLKH K tAVKH tKHAX tEVKH tKHEX SS tWVKH tKHWX SW SWx ZZ KHQX1 DQn Note not shown; assumes K tied out of phase ...
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JTAG Port Registers JTAG Pin Descriptions Pin Pin Name I/O Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate TCK Test Clock In from the falling edge of TCK. The TMS ...
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TDI TMS TCK Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded ...
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Tap Controller Instruction Set ID Register Contents Die Revision Code Bit # ...
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Test Logic Reset 1 0 Run Test Idle 0 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to ...
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Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the ...
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JTAG Port AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Notes: 1. Include scope and jig capacitance. 2. Test conditions as shown unless otherwise noted. JTAG TAP Instruction Set ...
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JTAG Port Recommended Operating Conditions and DC Characteristics Parameter 3.3 V Test Port Input High Voltage 3.3 V Test Port Input Low Voltage 2.5 V Test Port Input High Voltage 2.5 V Test Port Input Low Voltage TMS, TCK and ...
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TCK TDI TMS TDO Parallel SRAM input JTAG Port AC Electrical Characteristics Parameter Symbol TCK Cycle Time tTKC TCK Low to TDO Valid tTKQ TCK High Pulse Width tTKH TCK Low Pulse Width tTKL TDI & TMS Set Up Time ...
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Package Dimensions—119-Bump FPBGA (Package B, Variation 2 A1 TOP VIEW SEATING PLANE C Rev: 1.05 10/2005 ...
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... GS815018AB-333 GS815018AB-300 GS815018AB-250 512K x 36 GS815036AB-357 512K x 36 GS815036AB-333 512K x 36 GS815036AB-300 512K x 36 GS815036AB-250 GS815018AB-357I GS815018AB-333I GS815018AB-300I GS815018AB-250I 512K x 36 GS815036AB-357I 512K x 36 GS815036AB-333I 512K x 36 GS815036AB-300I 512K x 36 GS815036AB-250I GS815018AGB-357 GS815018AGB-333 ...
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Ordering Information Org Part Number GS815018AGB-300I GS815018AGB-250I 512K x 36 GS815036AGB-357I 512K x 36 GS815036AGB-333I 512K x 36 GS815036AGB-300I 512K x 36 GS815036AGB-250I Notes: 1. Customers requiring delivery in Tape and Reel should add ...
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Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; Types of Changes New Format or Content 8150xxA_r1 8150xxA_r1; 8150xxA_r1_01 8150xxA_r1_01; 8150xxA_r1_02 8150xxA_r1_02; 8150xxA_r1_03 8150xxA_r1_03; 8150xxA_r1_04 8150xxA_r1_04; 8150xxA_r1_05 Rev: 1.05 10/2005 Specifications cited are subject to change without notice. For latest ...