AS7C33128PFS18B-133TQC ALSC [Alliance Semiconductor Corporation], AS7C33128PFS18B-133TQC Datasheet - Page 5

• Manufacturer Part Number: AS7C33128PFS18B-133TQC
• Description: 3.3V 128K x 18 pipeline burst synchronous SRAM
• Manufacturer: ALSC [Alliance Semiconductor Corporation]

Signal descriptions
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to I
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, I
is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during t
MODE.
CLK
A,A0,A1
DQ[a,b]
CE0
CE1, CE2
ADSP
ADSC
ADV
GWE
BWE
BW[a,b]
OE
LBO
ZZ
NC
12/10/04; v.1.4
Signal
I
I
I/O
I
I
I
I
I
I
I
I
I
I
I
-
I/O
CLOCK
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
ASYNC
STATIC
SYNC
SYNC
ASYNC
-
PUS
Properties
, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE
SB2
is guaranteed after the time t
Clock. All inputs except OE, ZZ, LBO are synchronous to this clock.
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and OE is active.
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is
inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information.
Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled on clock
edges when ADSC is active or when CE0 and ADSP are active.
Address strobe (processor). Asserted LOW to load a new address or to enter standby mode.
Address strobe (controller). Asserted LOW to load a new address or to enter standby mode.
Burst advance. Asserted LOW to continue burst read/write.
Global write enable. Asserted LOW to write all 18 bits. When HIGH, BWE and BW[a,b]
control write enable.
Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a,b] inputs.
Write enables. Used to control write of individual bytes when GWE = HIGH and BWE =
LOW. If any of BW[a,b] is active with GWE = HIGH and BWE = LOW the cycle is a write
cycle. If all BW[a,b] are inactive, the cycle is a read cycle.
Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read
mode.
Selects Burst mode. When tied to V
order. When driven Low, device follows linear Burst order. This signal is internally pulled
High.
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
No connect
Alliance Semiconductor
ZZI
®
is met. After entering SNOOZE MODE, all inputs except ZZ
DD
Description
or left floating, device follows interleaved Burst
AS7C33128PFS18B
SB2
. The duration of
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