VRS51C1000-40-L RAMTRON [Ramtron International Corporation], VRS51C1000-40-L Datasheet - Page 14

• Manufacturer Part Number: VRS51C1000-40-L
• Description: Versa 8051 MCU with 64KB of IAP/ISP Flash
• Manufacturer: RAMTRON [Ramtron International Corporation]

Port P0 and P2 as Address and Data Bus
The output stage may receive data from two sources:
Internal Bus
When the ports are used as an address or data bus,
the special function registers P0 and P2 are
disconnected from the output stage, the 8 bits of the
P0 register are forced to 1 and the content of the P2
register remains constant.
Port 1
The P1 register controls the direction of the Port 1 I/O
pins. Writing a 1 into the P1.x bit (see following table)
of the P1 register configures the bit as an output,
presenting a logic 1 to the corresponding I/O pin, or
enables use of the I/O pin as an input. Writing a 0
activates the output “pull-down” transistor which will
force the corresponding I/O line to a logic Low.
T
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F
IGURE
ABLE
Write to
Register
Bit
7
6
5
4
3
2
1
0
P1.7
VRS51C1000
Read Register
7
o
o
20: P
Read Pin
8: P2 P
ORT
Mnemonic
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
The outputs of register P0 or the bus address
itself multiplexed with the data bus for P0.
The outputs of the P2 register or the high byte
(A8 through A15) of the bus address for the P2
port.
P1.6
ORT
6
1 R
EGISTER
S
TRUCTURE
P1.5
5
(P1) - SFR 90
D Flip-Flop
Description
For each bit of the P1 register correspond
to an I/O line:
0: Output transistor pull the line to 0V
1: The output transistor is blocked so the
pull-up bring the I/O to 5V.
Q
Q
P1.4
4
Control
H
P1.3
3
Address
P1.2
2
Vcc
X1
Pull-up
Network
P1.1
1
P1.0
IC Pin
0
Auxiliary Port 1 Functions
The Port 1 I/O pins are shared with the PWM outputs,
Timer 2 EXT and T2 inputs as shown below:
Port 3
structure of Port 3 is similar to that of Port 1.
T
Auxiliary P3 Port Functions
The Port 3 I/O pins are shared with the UART
interface, INT0 and the INT1 interrupts, Timer 0 and
Timer 1 inputs and finally the #WR and #RD lines
when external memory accesses are performed.
ABLE
Bit
7
6
5
4
3
2
1
0
Pin
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P3.7
7
21: P
ORT
Mnemonic
T2
T2EX
PWM0
PWM1
PWM2
PWM3
PWM4
Mnemonic
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
P3.6
6
3 R
EGISTER
P3.5
5
(P3) - SFR B0
Description
For each bit of the P3 register correspond
to an I/O line:
0: Output transistor pull the line to 0V
1: The output transistor is blocked so the
pull-up brings the I/O to 5V.
To configure P3 pins as input or use
alternate P3 function the corresponding bit
must be set to 1.
Function
Timer 2 counter input
Timer2 Auxiliary input
PWM0 output
PWM1 output
PWM2 output
PWM3 output
PWM4 output
P3.4
4
H
P3.3
3
page 14 of 48
P3.2
2
P3.1
1
P3.0
0