AM29DL400BB-120SF AMD [Advanced Micro Devices], AM29DL400BB-120SF Datasheet - Page 22

• Manufacturer Part Number: AM29DL400BB-120SF
• Description: 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

If the output is low (Busy), the device is actively
erasing or programming. (This includes program-
ming in the Erase Suspend mode.) If the output is
high (Ready), the device is ready to read array data,
is in the standby mode, or one of the banks is in the
erase-suspend-read mode.
Table 6 shows the outputs for RY/BY#.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any ad-
dress within the programming or erasing bank, and
is valid after the rising edge of the final WE# pulse in
the command sequence (prior to the program or
erase operation), and during the sector erase time-
out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address within
the programming or erasing bank cause DQ6 to tog-
gle. The system may use either OE# or CE# to
control the read cycles. When the operation is com-
plete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 µs, then returns to
reading array data. If not all selected sectors are
protected, the Embedded Erase algorithm erases the
unprotected sectors, and ignores the selected sec-
tors that are protected.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When a bank is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When that bank enters the Erase Suspend
mode, DQ6 stops toggling. However, the system
must also use DQ2 to determine which sectors are
erasing or erase-suspended. Alternatively, the sys-
tem can use DQ7 (see the subsection on DQ7:
Data# Polling).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the pro-
gram command sequence is written, then returns to
reading array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Table 6 shows the outputs for Toggle Bit I on DQ6.
Figure 6 shows the toggle bit algorithm. Figure 21 in
the “AC Characteristics” section shows the toggle bit
timing diagrams. Figure 22 shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on DQ2: Toggle Bit II.
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Am29DL400B
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, in-
dicates whether a particular sector is actively erasing
(that is, the Em bedde d Era se a lg orithm is i n
progress), or whether that sector is erase-sus-
pended. Toggle Bit II is valid after the rising edge of
the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to
control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-
suspended. DQ6, by comparison, indicates whether
the device is actively erasing, or is in Erase Suspend,
but cannot distinguish which sectors are selected for
erasure. Thus, both status bits are required for sec-
tor and mode information. Refer to Table 6 to
compare outputs for DQ2 and DQ6.
Figure 6 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains
the algorithm. See also the DQ6: Toggle Bit I subsec-
tion. Figure 21 shows the toggle bit timing diagram.
Figure 22 shows the differences between DQ2 and
DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 for the following discussion. When-
ever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row
to determine whether a toggle bit is toggling. Typi-
cally, the system would note and store the value of
the toggle bit after the first read. After the second
read, the system would compare the new value of
the toggle bit with the first. If the toggle bit is not
toggling, the device has completed the program or
erase operation. The system can read array data on
DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the sys-
tem determines that the toggle bit is still toggling,
the system also should note whether the value of
DQ5 is high (see the section on DQ5). If it is, the
system should then determine again whether the
toggle bit is toggling, since the toggle bit may have
stopped toggling just as DQ5 went high. If the toggle
bit is no longer toggling, the device has successfully
completed the program or erase operation. If it is
still toggling, the device did not completed the oper-
ation successfully, and the system must write the
reset command to return to reading array data.
The remaining scenario is that the system initially
determines that the toggle bit is toggling and DQ5
has not gone high. The system may continue to
monitor the toggle bit and DQ5 through successive
read cycles, determining the status as described in
the previous paragraph. Alternatively, it may choose
to perform other system tasks. In this case, the sys-
tem must start at the beginning of the algorithm
when it returns to determine the status of the opera-
tion (top of Figure 6).