AM29DL640D120 AMD [Advanced Micro Devices], AM29DL640D120 Datasheet - Page 4

• Manufacturer Part Number: AM29DL640D120
• Description: 64 Megabit CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Common Flash Memory Interface (CFI) . . . . . . . 20
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 24
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 29
October 7, 2004
Requirements for Reading Array Data ..................................... 9
Writing Commands/Command Sequences ............................ 10
Accelerated Program Operation ............................................. 10
Autoselect Functions .............................................................. 10
Simultaneous Read/Write Operations with Zero Latency ....... 10
Automatic Sleep Mode ........................................................... 11
RESET#: Hardware Reset Pin ............................................... 11
Output Disable Mode .............................................................. 11
Write Protect (WP#) ................................................................ 17
Temporary Sector Unprotect .................................................. 17
SecSi™ (Secured Silicon) Sector
Flash Memory Region ............................................................ 19
Hardware Data Protection ...................................................... 20
Low VCC Write Inhibit ............................................................ 20
Write Pulse “Glitch” Protection ............................................... 20
Logical Inhibit .......................................................................... 20
Power-Up Write Inhibit ............................................................ 20
Reading Array Data ................................................................ 24
Reset Command ..................................................................... 24
Autoselect Command Sequence ............................................ 24
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence .............................................................. 24
Byte/Word Program Command Sequence ............................. 25
Unlock Bypass Command Sequence ..................................... 25
Chip Erase Command Sequence ........................................... 26
Sector Erase Command Sequence ........................................ 26
Erase Suspend/Erase Resume Commands ........................... 27
DQ7: Data# Polling ................................................................. 29
DQ6: Toggle Bit I .................................................................... 30
DQ2: Toggle Bit II ................................................................... 31
Reading Toggle Bits DQ6/DQ2 .............................................. 31
DQ5: Exceeded Timing Limits ................................................ 31
Table 1. Am29DL640D Device Bus Operations ................................9
Table 2. Am29DL640D Sector Architecture ....................................11
Table 3. Bank Address ....................................................................14
Table 5. Am29DL640D Autoselect Codes, (High Voltage Method) 15
Table 6. Am29DL640D Boot Sector/Sector Block Addresses for Pro-
tection/Unprotection ........................................................................16
Table 7. WP#/ACC Modes ..............................................................17
Figure 1. Temporary Sector Unprotect Operation........................... 17
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 18
Figure 3. SecSi Sector Protect Verify.............................................. 20
Figure 4. Program Operation .......................................................... 26
Figure 5. Erase Operation............................................................... 27
Figure 6. Data# Polling Algorithm ................................................... 29
Figure 7. Toggle Bit Algorithm......................................................... 30
Am29DL640D
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 33
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 36
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
Erase And Programming Performance . . . . . . . 49
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 49
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 49
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 50
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 52
DQ3: Sector Erase Timer ....................................................... 31
Read-Only Operations ........................................................... 37
Hardware Reset (RESET#) .................................................... 38
Word/Byte Configuration (BYTE#) .......................................... 39
Erase and Program Operations .............................................. 40
Temporary Sector Unprotect .................................................. 45
Alternate CE# Controlled Erase and Program Operations ..... 47
FBE063—63-Ball Fine-Pitch Ball Grid Array (FBGA)
12 x 11 mm package .............................................................. 50
TS 048—48-Pin Standard TSOP ............................................ 51
Revision A (March 5, 2001) .................................................... 52
Revision A+1 (March 9, 2001) ................................................ 52
Revision B (August 10, 2001) ................................................. 52
Revision B+1 (August 30, 2001) ............................................. 52
Revision B+2 (October 11, 2001) ........................................... 52
Revision B+3 (November 5, 2001) ......................................... 52
Revision B+4 (April 15, 2002) ................................................. 52
Revision B+5 (August 19, 2002) ............................................. 52
Revision C (January 10, 2003) ............................................... 53
Revision C+1 (September 15, 2004) ...................................... 53
Table 13. Write Operation Status ................................................... 32
Figure 8. Maximum Negative Overshoot Waveform ...................... 33
Figure 9. Maximum Positive Overshoot Waveform........................ 33
Figure 10. I
Automatic Sleep Currents) ............................................................. 35
Figure 11. Typical I
Figure 12. Test Setup.................................................................... 36
Figure 13. Input Waveforms and Measurement Levels ................. 36
Figure 14. Read Operation Timings ............................................... 37
Figure 15. Reset Timings ............................................................... 38
Figure 16. BYTE# Timings for Read Operations............................ 39
Figure 17. BYTE# Timings for Write Operations............................ 39
Figure 18. Program Operation Timings.......................................... 41
Figure 19. Accelerated Program Timing Diagram.......................... 41
Figure 20. Chip/Sector Erase Operation Timings .......................... 42
Figure 21. Back-to-back Read/Write Cycle Timings ...................... 43
Figure 22. Data# Polling Timings (During Embedded Algorithms). 43
Figure 23. Toggle Bit Timings (During Embedded Algorithms)...... 44
Figure 24. DQ2 vs. DQ6................................................................. 44
Figure 25. Temporary Sector Unprotect Timing Diagram .............. 45
Figure 26. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 46
Figure 27. Alternate CE# Controlled Write (Erase/Program)
Operation Timings.......................................................................... 48
CC1
Current vs. Time (Showing Active and
CC1
vs. Frequency ............................................ 35
3