SMM153_10 SUMMIT [Summit Microelectronics, Inc.], SMM153_10 Datasheet - Page 7

• Manufacturer Part Number: SMM153_10
• Description: 10-bit Digital Differential Voltage and Current Monitor
• Manufacturer: SUMMIT [Summit Microelectronics, Inc.]

TIMING DIAGRAMS
Note 1:
the FAULT# pin state. Actual DC Hysteresis is derived from the equation: (V
Actual DC Hysteresis= (2.5V/1.25V)(0.003V)=6mV.
Note 2: Current sense accuracy depends on the current sense resistor tolerance. Kelvin sensing of the voltage drop across this resistor must be used to
guarantee accuracy. Accuracy at the low range of the current monitor ADC will be adversely impacted by offset errors.
Note 4: Voltage accuracy is only guaranteed for factory-programmed settings. Changing voltage from the value reflected in the customer specific CSIR
code may result in inaccuracies exceeding those specified above.
Note 5: Not 100% Production tested. Guaranteed by Design and/or characterization.
Note 6: All electrical parameters are guaranteed to function over the stated VDD, VCS and temperature range. Electrical parameters not specified as
"guaranteed by design" are tested with a VDD voltage required of the specific application. For example, if the device is to be operated at 3.3V and VCS
supply of 12V, it is tested with a VDD supply of 3.3V, +-10% and a VCS supply of 12V, +-10%.
Note 3: It is recommended that ADC reads occur with a frequency of not more than 250Hz.
Summit Microelectronics, Inc
T
Diagram.
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
TI
t
SCL
SDA
I
SDA
WR
SCL
LOW
HIGH
BUF
SU:STA
HD:STA
SU:STO
AA
DH
R
F
SU:DAT
HD:DAT
2
A
C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS – 100kHz
= 0°C to +70°C, VDD = 2.7V to 5.5V unless otherwise noted. All voltages are relative to GND. See Figure 3 Timing
(OUT)
V
(IN)
HYST
t
SU:STA
t
is measured with a 1.25V external voltage and is determined by subtracting Threshold Low from Threshold High, V
R
Description
SCL Clock Frequency
Clock Low Period
Clock High Period
Bus Free Time
Start Condition Setup Time
Start Condition Hold Time
Stop Condition Setup Time
Clock Edge to Data Valid
Data Output Hold Time
SCL and SDA Rise Time
SCL and SDA Fall Time
Data In Setup Time
Data In Hold Time
Noise Filter SCL and SDA
Write Cycle Time
t
AA
t
HD:STA
t
Figure 3. Basic I
F
t
t
HD:DAT
HIGH
2134 3.0 1/20/2010
2
C Serial Interface Timing
Before New Transmission, Note 5
SCL low to valid SDA (cycle n)
SCL low (cycle n+1) to SDA
change
Note 5
Note 5
Noise suppression
t
LOW
7
t
DH
IN(COMP1/2)
Conditions
t
/V
SU:DAT
REF
)(
V
HYST
). For example, if V
t
SU:STO
Min
250
4.7
4.0
4.7
4.7
4.0
4.7
0.2
0.2
0
0
IN(COMP1/2)
t
t
Typ
100
BUF
WR (For Write Operation Only)
/=2.5V and V
SMM153
Max
1000
100
300
3.5
TH
5
-V
TL
while monitoring
REF
Units
KHz
ms
μs
μs
μs
μs
μs
μs
μs
μs
=1.25V then
ns
ns
ns
ns
ns