EVAL-AD1928EB AD [Analog Devices], EVAL-AD1928EB Datasheet - Page 14

• Manufacturer Part Number: EVAL-AD1928EB
• Description: 2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec
• Manufacturer: AD [Analog Devices]

AD1928
ground connections with other unrelated digital output signals.
When the PLL is used, jitter in the reference clock is attenuated
above a certain frequency depending on the loop filter.
RESET AND POWER-DOWN
The function of the RST pin sets all the control registers to
their default settings. To avoid pops, reset does not power
down the analog outputs. After RST is deasserted and the PLL
acquires lock condition, an initialization routine runs inside the
AD1928. This initialization lasts for approximately 256 master
clock cycles.
The power-down bits in the PLL and Clock Control 0, DAC
Control 1, and ADC Control 1 registers power down the
respective sections. All other register settings are retained. The
reset pin, PD / RST , should be pulled low by an external resistor
to guarantee proper startup.
SERIAL CONTROL PORT
The AD1928 has an SPI control port that permits programming
and reading back of the internal control registers for the ADCs,
DACs, and clock system. There is also a standalone mode
Table 11. Standalone Mode Selection
ADC Clocks
Slave
Master
CLATCH
COUT
CCLK
CIN
t
COE
t
CLS
D23
CIN
0
0
t
CCP
D22
t
COD
D9
D9
t
CCH
COUT
0
1
Figure 11. Format of SPI Signal
t
t
CDS
CCL
D8
D8
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t
CDH
available for operation without serial control that is configured
at reset using the serial control pins. All registers are set to
default, except the internal master clock enable is set to 1
and ADC BCLK and LRCLK master/slave is set by the COUT
pin. Standalone mode only supports stereo mode with an I
data format and 256 f
details. It is recommended to use a weak pull-up resistor on
CLATCH in applications that have a microcontroller. This pull-
up resistor ensures that the AD1928 recognizes the presence of
a microcontroller.
The SPI control port of the AD1928 is a 4-wire serial control
port. The format is similar to the Motorola® SPI format, except
the input data-word is 24 bits wide. The serial bit clock and
latch can be completely asynchronous to the sample rate of the
ADCs and DACs. Figure 11 shows the format of the SPI signal.
The first byte is a global address with a read/write bit. For the
AD1928, the address is 0x04, shifted left 1 bit due to the R/ W
bit. The second byte is the AD1928 register address and the
third byte is the data.
CCLK
0
0
S
master clock rate. Refer to Table 11 for
t
CLH
CLATCH
0
0
D0
D0
t
COTS
2
S