EVAL-AD5398AEBZ AD [Analog Devices], EVAL-AD5398AEBZ Datasheet - Page 10

• Manufacturer Part Number: EVAL-AD5398AEBZ
• Description: 120 mA, Current Sinking, 10-Bit, I2C DAC
• Manufacturer: AD [Analog Devices]

AD5398A
THEORY OF OPERATION
The AD5398A is a fully integrated 10-bit DAC with 120 mA
output current sink capability and is intended for driving voice
coil actuators in applications such as lens autofocus, image sta-
bilization, and optical zoom. The circuit diagram is shown in
Figure 16. A 10-bit current output DAC coupled with Resistor R
generates the voltage that drives the noninverting input of the
operational amplifier. This voltage also appears across the R
resistor and generates the sink current required to drive the
voice coil.
The R and R
fore, the temperature coefficient and any nonlinearities over
temperature are matched and the output drift over temperature
is minimized. Diode D1 is an output protection diode.
SERIAL INTERFACE
The AD5398A is controlled using the industry-standard I
2-wire serial protocol. Data can be written to or read from
the DAC at data rates up to 400 kHz. After a read operation,
the contents of the input register are reset to all zeros.
I
An I
generate the serial clock (SCL), and read/write data on the serial
data line (SDA) to/from slave devices such as the AD5398A. On
all devices on an I
line and the SDA pin is connected to the SDA line. I
can only pull the bus lines low; pulling high is achieved by the
pull-up resistors, R
bus capacitance, and the maximum load current that the I
device can sink (3 mA for a standard device).
2
C BUS OPERATION
SDA
SCL
PD
2
C bus operates with one or more master devices that
AD5398A
INTERFACE
I
Figure 16. Circuit Diagram Showing Connection to
2
C SERIAL
DGND
SENSE
V
DD
resistors are interleaved and matched. There-
2
C bus, the SCL pin is connected to the SCL
P
. The value of R
REFERENCE
OUTPUT DAC
CURRENT
10-BIT
Voice Coil
DGND
P
R
depends on the data rate,
POWER-ON
RESET
R
SENSE
3.3Ω
D1
AGND
VOICE COIL
ACTUATOR
V
DD
2
C devices
I
SINK
V
2
2
C
BAT
C
SENSE
Rev. 0 | Page 10 of 16
When the bus is idle, SCL and SDA are both high. The master
device initiates a serial bus operation by generating a start
condition, which is defined as a high-to-low transition on the
SDA line while SCL is high. The slave device connected to the
bus responds to the start condition and shifts in the next eight
data bits under the control of the serial clock. These eight data
bits consist of a 7-bit address, plus a read/write bit, which is 0 if
data is to be written to a device, and 1 if data is to be read from a
device. Each slave device on an I
address. The address of the AD5398A is 0001100; however,
0001101, 0001110, and 0001111 address the part because the
last two bits are unused/don’t care (see Figure 18 and Figure 19).
another way of looking at it is that the write address of the
AD5398A is 0001 1000 (0x18) and the read address is 0001 1001
(0x19). Again, Bit 6 and Bit 7 of the address are unused, and,
therefore, the write addresses can also be 0x1A, 0x1C, and 0x1E,
and the read address can be 0x1B, 0x1D, and 0x1F (see
and
At the end of the address data, after the R/ W bit, the slave
device that recognizes its own address responds by generating
an acknowledge (ACK) condition. This is defined as the slave
device pulling SDA low while SCL is low before the ninth clock
pulse, and keeping it low during the ninth clock pulse. Upon
receiving an ACK, the master device can clock data into the
AD5398A in a write operation, or it can clock it out in a read
operation. Data must change either during the low period of the
clock, because SDA transitions during the high period define a
start condition as described previously, or during a stop condi-
tion as described in the
I
generates an ACK at the end of each block. The AD5398A
requires 10 bits of data; two data-words must be written to it
when a write operation occurs, or read from it when a read
operation occurs. At the end of a read or write operation, the
AD5398A acknowledges the second data byte. The master
generates a stop condition, defined as a low-to-high transition
on SDA while SCL is high, to end the transaction.
Because the address plus R/ W bit always equals eight bits of data,
2
C data is divided into blocks of eight bits, and the slave
V
Figure 19
DD
R
P
I
2
R
C MASTER
DEVICE
P
).
SDA
SCL
Figure 17. Typical I
AD5398A
Data Format
2
C bus must have a unique
I
2
DEVICE
C SLAVE
2
section.
C Bus
I
2
DEVICE
C SLAVE
Figure 18