EVAL-AD5398AEBZ AD [Analog Devices], EVAL-AD5398AEBZ Datasheet - Page 4

• Manufacturer Part Number: EVAL-AD5398AEBZ
• Description: 120 mA, Current Sinking, 10-Bit, I2C DAC
• Manufacturer: AD [Analog Devices]

AD5398A
AC SPECIFICATIONS
V
Table 2.
Parameter
Output Current Settling Time
Slew Rate
Major Code Change Glitch Impulse
Digital Feedthrough
1
2
3
TIMING SPECIFICATIONS
V
Table 3.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
C
1
2
3
Timing Diagram
SCL
1
2
3
4
5
6
7
8
9
10
11
Temperature range for the B version is –30°C to +85°C.
Guaranteed by design and characterization; not production tested.
See the Terminology section.
Guaranteed by design and characterization; not production tested.
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
C
b
falling edge.
DD
DD
2
SDA
b
SCL
is the total capacitance of one bus line in pF. t
= 2.7 V to 5.5 V, AGND = DGND = 0 V, R
= 2.7 V to 5.5 V. All specifications T
1
t
9
Limit at T
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
250
300
20 + 0.1 C
400
3
CONDITION
START
B Version
t
4
MIN
b
3
, T
t
MAX
3
MIN
R
and t
t
Unit
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns max
ns min
pF max
10
to T
t
F
6
L
are measured between 0.3 V
= 25 Ω connected to V
MAX
Min
Figure 2. 2-Wire Serial Interface Timing Diagram
, unless otherwise noted.
B Version
Typ
250
0.3
0.15
0.06
Description
SCL clock frequency
SCL cycle time
t
t
t
t
t
t
t
t
t
Can be CMOS driven
t
t
Capacitive load for each bus line
t
HIGH
LOW
HD, STA
SU, DAT
HD, DAT
SU, STA
SU, STO
BUF
R
F
F
2
, rise time of both SCL and SDA when receiving
, fall time of SDA when receiving
, fall time of both SCL and SDA when transmitting
Rev. 0 | Page 4 of 16
, bus free time between a stop condition and a start condition
, SCL low time
, SCL high time
1, 2
, setup time for repeated start
Max
, start/repeated start condition hold time
, data setup time
, stop condition setup time
, data hold time
t
11
t
DD
5
DD
Unit
μs
nA-sec
nA-sec
mA/μs
and 0.7 V
, unless otherwise noted.
IH MIN
DD
Test Conditions/Comments
V
¼ scale to ¾ scale change (0x100 to 0x300)
1 LSB change around major carry
.
DD
of the SCL signal) to bridge the undefined region of the SCL
= 5 V, R
CONDITION
REPEATED
START
t
7
L
= 25 Ω, L
t
4
L
= 680 μH
t
1
CONDITION
STOP
t
8