HY27SF161G2A HYNIX [Hynix Semiconductor], HY27SF161G2A Datasheet - Page 12

• Manufacturer Part Number: HY27SF161G2A
• Description: 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
• Manufacturer: HYNIX [Hynix Semiconductor]

HY27SF(08/16)1G2A Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
3. DEVICE OPERATION
3.1 Page Read.
Upon initial device power up, the device defaults to Read mode. This operation is also initiated by writing 00h and 30h
to the command register along with four address cycles. In two consecutive read operations, the second one does
need 00h command, which four address cycles and 30h command initiates that operation. Second read operation
always requires setup command if first read operation was executed using also random data out command.
Two types of operations are available: random read. The random read mode is enabled when the page address is
changed. The 2112 bytes (X8 device) or 1056 words (X16 device) of data within the selected page are transferred to
the data registers in less than 25us(tR). The system controller may detect the completion of this data transfer (tR) by
analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in
50ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device out-
put the data starting from the selected column address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random
data output command. The column address of next data, which is going to be out, may be changed to the address
which follows random data output command.
Random data output can be operated multiple times regardless of how many times it is done in a page.
Random data output is not available in cache read.
3.2 Page Program.
The device is programmed basically by page, but it does allow multiple partial page programming of a word or consec-
utive bytes up to 2112 (X8 device) or words up to 1056 (X16 device), in a single page program cycle.
The number of consecutive partial page programming operation within the same page without an intervening erase
operation must not exceed 4 times for main array (X8 device:1time/512byte, X16 device:1time/256word) and 4 times
for spare array (X8 device:1time/16byte ,X16 device:1time/8word).
The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading
period in which up to 2112 bytes (X8 device) or 1056 words (X16 device) of data may be loaded into the data register,
followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the four cycle
address inputs and then serial data. The words other than those to be programmed do not need to be loaded. The
device supports random data input in a page. The column address of next data, which will be entered, may be
changed to the address which follows random data input command (85h). Random data input may be operated multi-
ple times regardless of how many times it is done in a page.
The Page Program confirm command (10h) initiates the programming process. Writing 10h alone without previously
entering the serial data will not initiate the programming process. The P/E/R Controller automatically executes the
algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once
the program process starts, the Read Status Register command may be entered to read the status register. The system
controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit (I/O 6) of the
Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When
the Page Program is complete, the Write Status Bit (I/O 0) may be checked. The internal write verify detects only
errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command
mode until another valid command is written to the command register. Figure 14 details the sequence.
Rev 0.3 / Nov. 2006
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