HY27SF161G2A HYNIX [Hynix Semiconductor], HY27SF161G2A Datasheet - Page 22
HY27SF161G2A
Manufacturer Part Number
HY27SF161G2A
Description
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Manufacturer
HYNIX [Hynix Semiconductor]
Datasheet
1.HY27SF161G2A.pdf
(46 pages)
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Rev 0.3 / Nov. 2006
CLE Setup time
CLE Hold time
CE setup time
CE hold time
WE pulse width
ALE setup time
ALE hold time
Address to Data Loading
Data setup time
Data hold time
Write Cycle time
WE High hold time
Data Transfer from Cell to register
ALE to RE Delay
CLE to RE Delay
Ready to RE Low
RE Pulse Width
WE High to Busy
Read Cycle Time
RE Access Time
RE High to Output High Z
CE High to Output High Z
RE High Hold Time
Output High Z to RE low
CE Access Time
WE High to RE low
RE or CE High to Output Hold
Device Resetting Time (Read / Program / Erase)
Write Protection time
NOTE:
1. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us
2. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
3. Program / Erase Enable Operation : WP high to WE High.
4. tADL is the time from the WE rising edge of final address cycle to the WE rising of first data cycle.
Program / Erase Disable Operation : WP Low to WE High.
Parameter
Table 13: AC Timing Characteristics
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Symbol
t
t
ADL
t
WW
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WHR
t
t
t
t
t
t
t
t
t
RHZ
CHZ
REH
CLS
CLH
ALS
ALH
CLR
REA
t
CEA
RST
WC
WH
WB
WP
DH
t
OH
CS
CH
DS
AR
RR
RP
RC
IR
R
(4)
(3)
HY27SF(08/16)1G2A Series
Min
100
100
25
10
35
10
25
25
10
20
10
45
15
10
10
20
25
50
15
60
10
0
1.8V
olt
5/10/500
Max
100
25
30
50
50
45
(1)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
22
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