EVAL-AD7923CB2 AD [Analog Devices], EVAL-AD7923CB2 Datasheet - Page 17

• Manufacturer Part Number: EVAL-AD7923CB2
• Description: 4-Channel, 200 kSPS, 12-Bit ADC with Sequencer in 16-Lead TSSOP
• Manufacturer: AD [Analog Devices]

For example, if the AD7923 is operated in a continuous sam-
pling mode, with a throughput rate of 200 kSPS and an SCLK
of 20 MHz (AV
Shutdown Mode, i.e., if PM1 = 0 and PM0 = 1, then the power
consumption is calculated as follows:
The maximum power dissipation during conversion is 13.5 mW
(I
Auto Shutdown is one dummy cycle, i.e., 1 ms, and the remaining
conversion time is another cycle, i.e., 800 ns, then the AD7923
can be said to dissipate 13.5 mW for 1.8 ms during each con-
version cycle. For the remainder of the conversion cycle, 3.2 ms,
the part remains in Shutdown. The AD7923 can be said to
dissipate 2.5 mW for the remaining 3.2 ms of the conversion
cycle. If the throughput rate is 200 kSPS, the cycle time is
5 ms and the average power dissipated during each cycle is
(1.8/5) ¥ (13.5 mW) + (3.2/5) ¥ (2.5 mW) = 4.8616 mW.
Figure 15 shows the maximum power versus throughput rate
when using the Auto Shutdown Mode with 5 V and 3 V supplies.
REV. 0
DD
= 2.7 mA max, AV
0.01
0.1
10
1
DOUT
SCLK
0
Figure 15. Power vs. Throughput Rate
DIN
CS
20
DD
THREE-
STATE
AV
t
t
2
3
DD
= 5 V), and the device is placed in Auto
40
= 5V
ZERO
WRITE
60
DD
1
THROUGHPUT – kSPS
ZERO
= 5 V). If the power-up time from
80
SEQ1
t
9
DOUT
SCLK
2
100
2 IDENTIFICATION
ADD1
DIN
CS
DONTC
120
BITS
3
ADD0
t
140
4
1
DONTC
VALID DATA
Figure 16. Serial Interface Timing Diagram
160
Figure 17. General Timing Diagram
4
DB11
AV
16
ADD1
DD
180
t
6
= 3V
5
200
t
DB10
7
t
CONVERT
t
CYCLE
ADD0
t
10
6
5 s MIN
–17–
SERIAL INTERFACE
Figures 16 shows the detailed timing diagrams for serial inter-
facing to the AD7923. The serial clock provides the conversion
clock and controls the transfer of information to and from the
AD7923 during each conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode,
takes the bus out of three-state, and the analog input is sampled
at this point. The conversion is also initiated at this point and
will require 16 SCLK cycles to complete. The track-and-hold
will go back into track on the 14th SCLK falling edge as shown
in Figure 16 at Point B. On the 16th SCLK falling edge the
DOUT line will go back into three-state. If the rising edge of CS
occurs before 16 SCLKs have elapsed, the conversion will be
terminated and the DOUT line will go back into three-state and
the Control Register will not be updated; otherwise DOUT
returns to three-state on the 16th SCLK falling edge, as shown
in Figure 16.
Sixteen serial clock cycles are required to perform the conversion
process and to access data from the AD7923. For the AD7923,
the twelve bits of data are preceded by two leading zeros and
two channel address bits ADD1 and ADD0, identifying which
channel the result corresponds to. CS going low clocks out the
first leading zero to be read in by the microcontroller or DSP on
the first falling edge of SCLK. The first falling edge of SCLK
will also clock out the second leading zero to be read in by the
microcontroller or DSP on the second SCLK falling edge, and
so on. The remaining two address bits and 12-data bits are then
clocked out by subsequent SCLK falling edges beginning with
the first address bit ADD1, thus the second falling clock edge
on the serial clock has the second leading zero provided and also
clocks out address bit ADD1. The final bit in the data transfer is
valid on the 16th falling edge, having been clocked out on the
previous (15th) falling edge.
11
1
POWER-UP
DB4
CODING
12
16
DB3
DONTC
13
DB2
DONTC
1
VALID DATA
t
QUIET
B
14
t
5
DB1
MIN
16
DONTC
15
t
DB0
8
DONTC
16
t
11
THREE-
STATE
t
QUIET
AD7923