EVAL-ADAU1401EB AD [Analog Devices], EVAL-ADAU1401EB Datasheet - Page 24

• Manufacturer Part Number: EVAL-ADAU1401EB
• Description: SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs
• Manufacturer: AD [Analog Devices]

ADAU1401
I
Figure 22 shows the timing of a single-word write operation.
Every ninth clock, the ADAU1401 issues an acknowledge by
pulling SDA low.
Figure 23 shows the timing of a burst mode write sequence.
This figure shows an example where the target destination
registers are two bytes. The ADAU1401 knows to increment its
subaddress register every two bytes because the requested
subaddress corresponds to a register or memory area with a
2-byte word length.
The timing of a single-word read operation is shown in Figure 24.
Note that the first R/ W bit is 0, indicating a write operation. This is
because the subaddress still needs to be written to set up the
internal address. After the ADAU1401 acknowledges the receipt
of the subaddress, the master must issue a repeated start command
followed by the chip address byte with the R/ W set to 1 (read).
This causes the ADAU1401 SDA to reverse and begin driving
S
S
S
S
2
C Read and Write Operations
Chip address,
R/W = 0
Chip address,
R/W = 0
Chip address,
R/W = 0
Chip address,
R/W = 0
AS
AS
AS
AS
Subaddress
high
Subaddress high
Subaddress
high
Subaddress
high
AS
AS
AS
Subaddress
low
AS
Subaddress
low
Subaddress
low
Subaddress low
Figure 22. Single-Word I
Figure 24. Single-Word I
Figure 23. Burst Mode I
Figure 25. Burst Mode I
AS
Rev. 0 | Page 24 of 52
AS
AS
S
Data-
Word 1,
Byte 1
S
Chip address,
R/W = 1
AS
2
2
2
2
C Write Format
C Read Format
C Write Format
C Read Format
Chip address,
R/W = 1
data back to the master. The master then responds every ninth
pulse with an acknowledge pulse to the ADAU1401.
Figure 25 shows the timing of a burst mode read sequence. This
figure shows an example where the target read registers are two
bytes. The ADAU1401 increments its subaddress every two bytes
because the requested subaddress corresponds to a register or
memory area with word lengths of two bytes. Other addresses
may have word lengths ranging from one to five bytes. The
ADAU1401 always decodes the subaddress and sets the auto-
increment circuit so that the address increments after the
appropriate number of bytes.
Figure 22 to Figure 25 use the following abbreviations:
S = start bit
P = stop bit
AM = acknowledge by master
AS = acknowledge by slave
Data Byte 1
AS
Data-
Word 1,
Byte 2
AS
AS
AS
Data
Byte 1
AS
Data-
Word 1,
Byte 1
Data Byte 2
Data-
Word 2,
Byte 1
AM
Data
Byte 2
AM
AS
…
Data-
Word 1,
Byte 2
Data-
Word 2,
Byte 2
…
AS
AM
Data Byte N
AM
AS
Data
Byte N
…
…
P
P
P
P