EVAL-ADV7533-SAZ AD [Analog Devices], EVAL-ADV7533-SAZ Datasheet - Page 5

• Manufacturer Part Number: EVAL-ADV7533-SAZ
• Description: MIPI/DSI Receiver
• Manufacturer: AD [Analog Devices]

Parameter
AC SPECIFICATIONS
AUDIO AC TIMING
CEC
I
1
2
3
4
2
See the
12 MHz crystal for default register settings.
Only applies to S/PDIF if external MCLK is used.
I
C INTERFACE
2
C data rates of 100 KHz and 400 KHz are supported.
Transmitter Total Power
TMDS Output Clock Frequency
TMDS Output Clock Duty Cycle
TMDS Differential Swing
Differential Output Timing
SCLK Duty Cycle
I
I
LRCLK Setup Time, t
LRCLK Hold Time, t
CEC_CLK Frequency
CEC_CLK Accuracy
CEC_CLK Duty Cycle
SCL Clock Frequency
SDA Setup Time, t
SDA Hold Time, t
Setup for Start, t
Hold Time for Start, t
Setup for Stop, t
Bus Free Between Stop and Start, t
SCL High, t
SCL Low, t
2
2
S, S/PDIF Setup, t
S, S/PDIF Hold Time, t
AVDD
V1P2 (1.2 V)
A2VDD
PVDD
V3P3—HDMI/HDCP Memory
V1P2 = 1.2 V
V1P2 = 1.8 V
Low-to-High Transition Time
High-to-Low Transition Time
When N = Even Number
When N = Odd Number
Explanation of Test Levels
LOW
HIGH
2
STOSU
STASU
DHO
DSU
ASU
AHLD
ASU
3
STAH
AHLD
section.
BUF
Conditions
HDMI analog core (24 bits at
720p)
HDMI/DSI digital core (DSI 30
bits/HDMI 24 bits at 720p)
MIPI DPHY (30 bits/three
lanes/720p)
HDMI PLL (24 bits at 720p)
HDMI HDCP memory
720p, 30-bit DSI in; 720p, 36-bit
HDMI out; typical random
pattern with CSC enabled,
HDCP enabled, audio enabled
Rev. 0 | Page 5 of 12
Temp
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
25°C
25°C
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test
Level
IV
IV
IV
IV
IV
IV
VI
IV
IV
VII
VII
VII
IV
IV
IV
IV
IV
IV
VIII
VIII
VIII
VIII
VIII
VIII
VIII
VIII
VIII
VIII
VIII
VIII
1
Min
20
48
800
75
75
49
2
2
2
2
3
−2
40
100
100
0.6
0.6
0.6
1.3
0.6
1.3
40
Typ
11
39
12
11
0.3
120
1000
175
175
50
50
12
ADV7533BCBZ
Max
154
204
112
52
1200
60
51
100
+2
60
400
4
ADV7533
ps
ns
ns
μs
μs
μs
μs
μs
Unit
mA
mA
mA
mA
mA
mW
mW
MHz
%
mV
ps
%
%
ns
ns
ns
ns
MHz
%
%
kHz
μs