AM29LV641GH53R SPANSION [SPANSION], AM29LV641GH53R Datasheet - Page 4

• Manufacturer Part Number: AM29LV641GH53R
• Description: 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O Control
• Manufacturer: SPANSION [SPANSION]

GENERAL DESCRIPTION
The Am29LV641G are 64 Mbit, 3.0 volt (3.0 V to 3.6 V)
single power supply flash memory devices organized
as 4,194,304 words. Data appears on DQ15–DQ0.
These devices are designed to be programmed in-sys-
tem with the standard system 3.0 volt V
12.0 volt V
ations. The device can also be programmed in stan-
dard EPROM programmers.
Access times of 55 regulated volage and 70 ns full
voltage range are available for applications where V
≥ V
T S O P a n d r e v e r s e T S O P p a c k a g e s . T h e
Am29LV640GU is offered in a 63-ball Fine-pitch BGA
package, and a 64-ball Fortified BGA. To eliminate bus
contention each device has separate chip enable
(CE#), write enable (WE#) and output enable (OE#)
controls.
Each device requires only a single 3.0 volt power
supply (2.7 V to 3.6 V) for both read and write func-
tions. Internally generated and regulated voltages are
provided for the program and erase operations.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timing. Register con-
tents serve as inputs to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already pro-
grammed) before executing the erase operation. Dur-
ing erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The VersatileI/O™ (V
tem to set the voltage levels that the device generates
at its data outputs and the voltages tolerated at its
data inputs to the same voltage level that is asserted
on the V
V or 3 V system environment as required.
The host system can detect whether a program or
erase operation is complete by reading the DQ7
(Data# Polling) or DQ6 (toggle) status bits. After a
program or erase cycle has been completed, the de-
5
CC
. The Am29LV641GH/L is offered in 48-pin
IO
PP
pin. This allows the device to operate in 1.8
is not required for program or erase oper-
IO
) control allows the host sys-
A D V A N C E
CC
supply. A
Am29LV641G
IO
I N F O R M A T I O N
vice is ready to read array data or accept another
command.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
V
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
The Erase Suspend/Erase Resume feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved. The Program Suspend/Program
Resume feature enables the host system to pause a
program operation in a given sector to read any other
sector and then complete the program operation.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to
the system reset circuitry. A system reset would thus
also reset the device, enabling the system micropro-
cessor to read boot-up firmware from the Flash mem-
ory device.
The device offers a standby mode as a power-saving
feature. Once the system places the device into the
standby mode power consumption is greatly reduced.
The SecSi ™ (Secured Silicon) Sector provides an
minimum 128-word area for code or data that can be
permanently protected. Once this sector is protected,
no further programming or erasing within the sector
can occur.
The Write Protect (WP#) feature protects the first or
last sector by asserting a logic low on the WP# pin.
The protected sector will still be protected even during
accelerated programming. (Am29LV641GH/L only)
The accelerated program (ACC) feature allows the
system to program the device at a much faster rate.
When ACC is pulled high to V
Unlock Bypass mode, enabling the user to reduce the
time needed to do the program operation. This feature
is intended to increase factory throughput during sys-
tem production, but may also be used in the field if de-
sired.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunnelling.
The data is programmed using hot electron injection.
CC
detector that automatically inhibits write opera-
HH
, the device enters the
June 14, 2005