CY7C13645JC Cypress Semiconductor Corporation., CY7C13645JC Datasheet

CY7C13645JC

Manufacturer Part Number

CY7C13645JC

Description

PLCC-52

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY7C13655JI.pdf (15 pages)

Specifications of CY7C13645JC

Date_code

04+

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Features

■

Notes

Cypress Semiconductor Corporation

Document #: 38-06031 Rev. *E

1. CY7C136 and CY7C136A are functionally identical.

2. CY7C132/CY7C136/CY7C136A (Master): BUSY is open drain output and requires pull up resistor. CY7C142/CY7C146 (Slave): BUSY is input.

3. Open drain outputs; pull up resistor required.

True dual-ported memory cells that enable simultaneous reads

of the same memory location

2K x 8 organization

0.65 micron CMOS for optimum speed and power

High speed access: 15 ns

Low operating power: I

Fully asynchronous operation

Automatic power down

Master CY7C132/CY7C136/CY7C136A

bus width to 16 or more bits using slave CY7C142/CY7C146

BUSY output flag on CY7C132/CY7C136/CY7C136A;

BUSY input on CY7C142/CY7C146

INT flag for port to port communication (52-Pin PLCC/PQFP

versions)

CY7C136, CY7C136A, and CY7C146 available in 52-pin

PLCC and 52-pin PQFP packages

Pb-free packages available

Logic Block Diagram

BUSY

INT

R/W

I/O

10L

[2]

= 110 mA (maximum)

[3]

[1]

DECODER

ADDRESS

•

easily expands data

R/W

198 Champion Court

CONTROL

I/O

(7C132/7C136 ONLY)

(7C136/7C146 ONLY)

INTERRUPTLOGIC

ARBITRATION

MEMORY

ARRAY

LOGIC

AND

Functional Description

The CY7C132, CY7C136, CY7C136A, CY7C142, and CY7C146

are high speed CMOS 2K x 8 dual-port static RAMs. Two ports

are provided to permit independent access to any location in

memory. The CY7C132, CY7C136, and CY7C136A can be used

as either a standalone 8-bit dual-port static RAM or as a

MASTER

CY7C142/CY7C146 SLAVE dual-port device. They are used in

systems that require 16-bit or greater word widths. This is the

solution to applications that require shared or buffered data, such

as cache memory for DSP, bit-slice, or multiprocessor designs.

Each port has independent control pins; chip enable (CE), write

enable (R/W), and output enable (OE). BUSY flags are provided

on each port. In addition, an interrupt flag (INT) is provided on

each port of the 52-pin PLCC version. BUSY signals that the port

is trying to access the same location currently being accessed

by the other port. On the PLCC version, INT is an interrupt flag

indicating that data is placed in an unique location (7FF for the

left port and 7FE for the right port).

An automatic power down feature is controlled independently on

each port by the chip enable (CE) pins.

CONTROL

2K x 8 Dual-Port Static RAM

•

I/O

DECODER

San Jose

ADDRESS

R/W

CY7C136A, CY7C142, CY7C146

dual-port

CA 95134-1709

RAM,

CY7C132, CY7C136

INT

R/W

I/O

BUSY

10R

[3]

[2]

conjunction

Revised March 24, 2009

•

408-943-2600

with

the

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