CY7C19955DMB Cypress Semiconductor Corporation., CY7C19955DMB Datasheet
CY7C19955DMB
Manufacturer Part Number
CY7C19955DMB
Description
CDIP
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
1.CY7C19920DMB.pdf
(11 pages)
Specifications of CY7C19955DMB
Date_code
07+
Cypress Semiconductor Corporation
Document #: 38-05160 Rev. *B
Features
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
CE
WE
• High speed
• Fast t
• CMOS for optimum speed/power
• Low active power
• Low standby power
• 2V data retention (“L” version only)
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• Available in pb-free 28-pin TSOP I and 28-pin (300-Mil)
OE
Logic Block Diagram
— 12 ns
— 495 mW (Max, “L” version)
— 0.275 mW (Max, “L” version)
Molded DIP
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
9
DOE
INPUT BUFFER
DECODER
COLUMN
ARRAY
32K x 8
POWER
DOWN
•
198 Champion Court
L
L
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Functional Description
The CY7C199 is a high-performance CMOS static RAM
organized as 32,768 words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE) and active
LOW Output Enable (OE) and tri-state drivers. This device has
an automatic power-down feature, reducing the power
consumption by 81% when deselected. The CY7C199 is in the
standard 300-mil-wide DIP, SOJ, and LCC packages.
An active LOW Write Enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O
addressed by the address present on the address pins (A
through A
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. A die coat is used to improve alpha immunity.
0
1
2
3
4
5
6
7
0
through I/O
–12
160
•
V
12
10
WE
A
A
OE
A
A
A
A
CC
A
A
A
A
A
10
11
14
1
2
3
4
5
6
7
8
9
San Jose
). Reading the device is accomplished by selecting
22
23
24
25
26
27
28
1
2
3
4
5
6
7
Pin Configurations
7
GND
) is written into the memory location
I/O
I/O
I/O
A
A
A
A
A
,
A
A
A
A
A
10
11
12
13
14
5
6
7
8
9
0
1
2
CA 95134-1709
0.05
32K x 8 Static RAM
–15
155
15
90
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Top View
(not to scale)
DIP
Top View
TSOP I
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Revised August 3, 2006
V
WE
A
A
A
OE
A
CE
I/O
I/O
I/O
I/O
I/O
A
CC
3
2
1
0
4
3
7
6
5
4
–20
150
20
10
•
CY7C199
408-943-2600
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Unit
mA
mA
ns
A
CE
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
A
A
A
0
14
13
12
7
6
5
4
3
2
1
0
0
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