74AUP1G97GM,115 NXP Semiconductors, 74AUP1G97GM,115 Datasheet - Page 4
![IC CONFIG MULT-FUNC GATE 6-XSON](/photos/1/39/13915/6-xson_sot886_pkg_sml.jpg)
74AUP1G97GM,115
Manufacturer Part Number
74AUP1G97GM,115
Description
IC CONFIG MULT-FUNC GATE 6-XSON
Manufacturer
NXP Semiconductors
Series
74AUPr
Datasheet
1.74AUP1G97GM115.pdf
(22 pages)
Specifications of 74AUP1G97GM,115
Number Of Circuits
1
Package / Case
6-XSON (Micropak™), SOT-886
Logic Type
Configurable Multiple Function
Number Of Inputs
3
Schmitt Trigger Input
Yes
Output Type
Single-Ended
Current - Output High, Low
4mA, 4mA
Voltage - Supply
0.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Product
MUX Gates
Logic Family
74AUP
High Level Output Current
- 4 mA
Low Level Output Current
4 mA
Propagation Delay Time
23 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
0.8 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 125 C
Output Current
20 mA
Output Voltage
3.6 V
Power Dissipation
250 mW
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-4390-2
74AUP1G97GM-G
74AUP1G97GM-G
935279963115
74AUP1G97GM-G
74AUP1G97GM-G
935279963115
NXP Semiconductors
Table 5.
74AUP1G97
Product data sheet
Logic function
2-input MUX
2-input AND
2-input OR with one input inverted
2-input NAND with one input inverted
2-input AND with one input inverted
2-input NOR with one input inverted
2-input OR
Inverter
Buffer
Fig 5.
Fig 7.
Fig 9.
B
A
C
2-input MUX
2-input NAND gate with input A inverted or
2-input OR gate with input C inverted
2-input OR gate
C
C
C
A
A
B
Function selection table
7.1 Logic configurations
Y
Y
Y
Y
A
B
B
A
1
2
3
1
2
3
1
2
3
6
5
4
6
5
4
All information provided in this document is subject to legal disclaimers.
6
5
4
001aae004
001aae006
001aae002
C
Y
C
Y
C
Y
V
V
CC
CC
V
CC
Rev. 6 — 10 January 2011
Figure
see
see
see
see
see
see
see
see
see
Fig 6.
Fig 8.
Fig 10. Inverter
Figure 5
Figure 6
Figure 7
Figure 7
Figure 8
Figure 8
Figure 9
Figure 10
Figure 11
Low-power configurable multiple function gate
2-input AND gate
2-input NOR gate with input B inverted or
2-input AND gate with input C inverted
C
C
C
A
B
B
C
Y
Y
Y
Y
A
B
74AUP1G97
1
2
3
1
2
3
1
2
3
6
5
4
001aae007
6
5
4
6
5
4
© NXP B.V. 2011. All rights reserved.
001aae003
001aae005
C
Y
V
C
Y
C
Y
CC
V
V
CC
CC
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