AM27C1024-70DI Advanced Micro Devices, AM27C1024-70DI Datasheet

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AM27C1024-70DI

Manufacturer Part Number
AM27C1024-70DI
Description
Manufacturer
Advanced Micro Devices
Datasheet

Specifications of AM27C1024-70DI

Package
DIP
Date_code
05+/06+

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Am27C1024
1 Megabit (65 K x 16-Bit) CMOS EPROM
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
The Am27C1024 is a 1 Megabit, ultraviolet erasable
programmable read-only memory. It is organized as 64
Kwords by 16 bits per word, operates from a single
+5 V supply, has a static standby mode, and features
fast single address location programming. Products are
available in windowed ceramic DIP packages, as well
as plastic one time programmable (OTP) PDIP and
PLCC packages.
Data can be typically accessed in less than 55 ns, al-
lowing high-performance microprocessors to operate
without any WAIT states. The device offers separate
Output Enable (OE#) and Chip Enable (CE#) controls,
BLOCK DIAGRAM
Fast access time
— Speed options as fast as 55 ns
Low power consumption
— 20 µA typical CMOS standby current
JEDEC-approved pinout
— 40-Pin DIP/PDIP
— 44-Pin PLCC
Single +5 V power supply
FINAL
A0–A15
Address
Inputs
PGM#
OE#
CE#
Output Enable
Chip Enable
Prog Logic
V
V
V
Decoder
Decoder
CC
SS
PP
and
Y
X
thus eliminating bus contention in a multiple bus micro-
processor system.
AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 125 mW in active mode,
and 100 µW in standby mode.
All signals are TTL levels, including programming sig-
nals. Bit locations may be programmed singly, in
blocks, or at random. The device supports AMD’s
Flashrite programming algorithm (100 µs pulses), re-
sulting in a typical programming time of 8 seconds.
100% Flashrite™ programming
— Typical programming time of 8 seconds
Latch-up protected to 100 mA from –1 V to
V
High noise immunity
Versatile features for simple interfacing
— Both CMOS and TTL input/output compatibility
— Two line control functions
10% power supply tolerance standard
CC
+ 1 V
Data Outputs
DQ0–DQ15
1,048,576
Buffers
Bit Cell
Output
Gating
Matrix
Y
Publication# 06780
Issue Date: May 1998
Rev: J Amendment/0
06780J-1

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