74AUP1G3208GW,125 NXP Semiconductors, 74AUP1G3208GW,125 Datasheet - Page 4

• Manufacturer Part Number: 74AUP1G3208GW,125
• Description: IC 3-IN OR-AND GATE LP SC-88
• Manufacturer: NXP Semiconductors
• Series: 74AUPr

Specifications of 74AUP1G3208GW,125

• Logic Type: AND/OR Gate
• Number Of Circuits: 1
• Number Of Inputs: 3 Input (2, 1)
• Schmitt Trigger Input: Yes
• Output Type: Single-Ended
• Current - Output High, Low: 4mA, 4mA
• Voltage - Supply: 0.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: SC-70-6, SC-88, SOT-363
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74AUP1G3208GW-G; 74AUP1G3208GW-G; 935280616125

NXP Semiconductors
Table 5.
8. Limiting values
Table 6.
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
[1]
[2]
74AUP1G3208
Product data sheet
Logic function
2-input AND
2-input OR
3-input gate with the Boolean function: Y = (A + B) × C
Symbol
V
I
V
I
V
I
I
I
T
P
IK
OK
O
CC
GND
Fig 5.
Fig 7.
stg
CC
I
O
tot
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SC-88 packages: above 87.5 °C the value of P
For XSON6 packages: above 118 °C the value of P
2-input AND gate
2-input OR gate
Function selection table
Limiting values
C
B
A
B
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
7.1 Logic configurations
Y
Y
A
B
B
1
2
3
1
2
3
6
5
4
6
5
4
001aad504
001aad502
All information provided in this document is subject to legal disclaimers.
Conditions
V
V
Active mode and Power-down mode
V
T
Y
amb
I
O
O
C
Y
V
< 0 V
V
< 0 V
= 0 V to V
CC
CC
= −40 °C to +125 °C
tot
tot
Rev. 3 — 11 October 2010
derates linearly with 4.0 mW/K.
derates linearly with 7.8 mW/K.
CC
Figure
see
see
see
Fig 6.
Fig 8.
Figure 5
Figure 7
Figure 8
A
B
C
2-input AND gate
3-input gate with the Boolean function:
Y = (A + B) × C
A
C
and
Figure 6
[1]
[1]
[2]
Low-power 3-input OR-AND gate
Min
−0.5
−50
−0.5
−50
−0.5
-
-
−50
−65
-
Y
74AUP1G3208
Y
A
A
B
1
2
3
Max
+4.6
-
+4.6
-
+4.6
±20
50
-
+150
250
1
2
3
6
5
4
001aad503
© NXP B.V. 2010. All rights reserved.
6
5
4
C
Y
001aad505
V
CC
C
Y
V
CC
Unit
V
mA
V
mA
V
mA
mA
mA
°C
mW
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