74LVQ373SJ Fairchild Semiconductor, 74LVQ373SJ Datasheet

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74LVQ373SJ

Manufacturer Part Number
74LVQ373SJ
Description
IC LATCH TRANSP OCT 3ST 20-SOP
Manufacturer
Fairchild Semiconductor
Series
74LVQr
Datasheet

Specifications of 74LVQ373SJ

Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
2 V ~ 6 V
Independent Circuits
1
Delay Time - Propagation
8ns
Current - Output High, Low
12mA, 12mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
© 2001 Fairchild Semiconductor Corporation
74LVQ373SC
74LVQ373SJ
74LVQ373QSC
74LVQ373
Low Voltage Octal Transparent Latch
with 3-STATE Outputs
General Description
The LVQ373 consists of eight latches with 3-STATE out-
puts for bus organized system applications. The latches
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is low, the data satisfying the input timing
requirements is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the bus
output is in the high impedance state.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Pin Descriptions
Order Number
D
LE
OE
O
Pin Names
0
0
–D
–O
7
7
Package Number
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Latch Outputs
IEEE/IEC
MQA20
M20B
M20D
Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
DS011359
Features
Connection Diagram
Truth Table
H
Z
O
0
Ideal for low power/low noise 3.3V applications
Implements patented EMI reduction circuitry
Available in SOIC JEDEC, SOIC EIAJ and QSOP
packages
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Improved latch-up immunity
Guaranteed incident wave switching into 75
4 kV minimum ESD immunity
High Impedance
HIGH Voltage Level
Previous O
LE
X
H
H
L
Package Description
0
before HIGH to Low transition of Latch Enable
Inputs
OE
H
L
L
L
L
X
LOW Voltage Level
Immaterial
February 1992
Revised June 2001
D
H
X
L
X
n
www.fairchildsemi.com
Outputs
O
O
Z
H
L
n
0

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74LVQ373SJ Summary of contents

Page 1

... Ordering Code: Order Number Package Number 74LVQ373SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVQ373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVQ373QSC MQA20 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Devices also available in Tape and Reel. Specify by appending suffix letter “ ...

Page 2

Functional Description The LVQ373 contains eight D-type latches with 3-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the D inputs enters the latches. In this con- n dition the latches are transparent, i.e., a latch ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Diode Current ( 0. 0. Input Voltage ( Output Diode Current ( ...

Page 4

AC Electrical Characteristics Symbol Parameter t Propagation Delay PHL PLH Propagation Delay PLH PHL n t Output Enable Time PZL t PZH t Output Disable Time PHZ t PLZ ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M20D 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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