74ACTQ573SC Fairchild Semiconductor, 74ACTQ573SC Datasheet

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74ACTQ573SC

Manufacturer Part Number
74ACTQ573SC
Description
IC LATCH OCTAL 3STATE 20SOIC
Manufacturer
Fairchild Semiconductor
Series
74ACTQr
Datasheets

Specifications of 74ACTQ573SC

Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
4.5 V ~ 5.5 V
Independent Circuits
1
Delay Time - Propagation
6.5ns
Current - Output High, Low
24mA, 24mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (7.5mm Width)
Dc
99+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
© 1999 Fairchild Semiconductor Corporation
74ACQ573MTC
74ACQ573SC
74ACQ573SJ
74ACQ573PC
74ACTQ573SC
74ACTQ573SJ
74ACTQ573QSC
74ACTQ573PC
74ACQ573 • 74ACTQ573
Quiet Series
General Description
The ACQ/ACTQ573 is a high-speed octal latch with buff-
ered common Latch Enable (LE) and buffered common
Output Enable (OE) inputs. The ACQ/ACTQ573 is func-
tionally identical to the ACQ/ACTQ373 but with inputs and
outputs on opposite sides of the package. The ACQ/ACTQ
utilizes Fairchild’s Quiet Series
quiet output switching and improved dynamic threshold
performance. FACT Quiet Series
control and undershoot corrector in addition to a split
ground bus for superior performance.
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
FACT , Quiet Series , FACT Quiet Series , and GTO
Order Number
Package Number
MQA20
MTC20
IEEE/IEC
M20B
M20D
M20B
M20D
N20A
N20A
Octal Latch with 3-STATE Outputs
technology to guarantee
features GTO
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
are trademarks of Fairchild Semiconductor Corporation
DS010633
output
Features
Connection Diagram
Pin Descriptions
I
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Guaranteed pin-to-pin skew AC performance
Improved latch-up immunity
Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
Outputs source/sink 24 mA
CC
and I
Package Description
D
LE
OE
O
Pin Names
0
0
–D
–O
OZ
7
7
reduced by 50%
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Latch Outputs
January 1990
Revised November 1999
Description
www.fairchildsemi.com

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74ACTQ573SC Summary of contents

Page 1

... MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACQ573PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 74ACTQ573SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 74ACTQ573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide ...

Page 2

Functional Description The ACQ/ACTQ573 contains eight D-type latches with 3- STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the D inputs enters the latches. In this con- n dition the latches are transparent, i.e., a ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Diode Current ( 0. 0. Input Voltage ( Output Diode Current ( ...

Page 4

DC Electrical Characteristics for ACQ Symbol Parameter V Quiet Output OLV Minimum Dynamic Minimum HIGH Level IHD Dynamic Input Voltage V Maximum LOW Level ILD Dynamic Input Voltage Note 2: All outputs loaded; thresholds on input associated ...

Page 5

AC Electrical Characteristics for ACQ Symbol Parameter t Propagation Delay PHL PLH Propagation Delay PLH PHL n t Output Enable Time PZL t PZH t Output Disable Time PHZ ...

Page 6

AC Operating Requirements for ACTQ Symbol Parameter t Setup Time, HIGH or LOW Hold Time, HIGH or LOW Pulse Width, HIGH W Note 18: Voltage Range 5.0 ...

Page 7

FACT Noise Characteristics The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. Equipment: Hewlett Packard ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body www.fairchildsemi.com Package Number M20B 8 ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 9 www.fairchildsemi.com ...

Page 10

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide www.fairchildsemi.com Package Number MQA20 10 ...

Page 11

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 11 www.fairchildsemi.com ...

Page 12

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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