74AHCT573PW,118 NXP Semiconductors, 74AHCT573PW,118 Datasheet - Page 11

• Manufacturer Part Number: 74AHCT573PW,118
• Description: IC OCT D TRANSP LTCH 3ST 20TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74AHCTr

Specifications of 74AHCT573PW,118

• Logic Type: D-Type Transparent Latch
• Package / Case: 20-TSSOP
• Circuit: 8:8
• Output Type: Tri-State
• Voltage - Supply: 4.5 V ~ 5.5 V
• Independent Circuits: 1
• Delay Time - Propagation: 3.5ns
• Current - Output High, Low: 8mA, 8mA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 8
• Logic Family: AHCT
• Polarity: Non-Inverting
• High Level Output Current: - 8 mA
• Low Level Output Current: 8 mA
• Propagation Delay Time: 3.9 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-4468-2; 74AHCT573PW-T; 74AHCT573PW-T; 935263074118

NXP Semiconductors
Table 8.
74AHC_AHCT573
Product data sheet
Type
74AHC573
74AHCT573
Fig 9.
Fig 10. Data set-up and hold times
Measurement points are given in
V
Enable and disable times
Measurement points are given in
V
The shaded areas indicate when the input is permitted to change for predicable output performance.
OL
OL
Measurement points
and V
and V
OH
OH
are typical voltage output levels that occur with the output load.
are typical voltage output levels that occur with the output load.
HIGH-to-OFF
OFF-to-HIGH
LOW-to-OFF
OFF-to-LOW
Qn output
Qn output
Dn input
LE input
Input
V
0.5  V
1.5 V
OE input
M
GND
GND
CC
V
V
GND
GND
V
V
I
I
Table
Table
V
CC
OH
OL
V
All information provided in this document is subject to legal disclaimers.
I
8.
8.
Rev. 6 — 25 November 2010
V
M
enabled
V
outputs
M
t
t
su
PLZ
t
Output
V
0.5  V
0.5  V
PHZ
M
t
V
h
V
M
CC
CC
X
V
Y
74AHC573; 74AHCT573
disabled
outputs
V
V
V
t
Octal D-type transparant latch; 3-state
X
OL
OL
t
PZL
t
su
PZH
+ 0.3 V
+ 0.3 V
V
t
M
h
V
M
mna814
outputs
enabled
mna813
V
V
V
Y
OH
OH
© NXP B.V. 2010. All rights reserved.
 0.3 V
 0.3 V
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