74HC373D,653 NXP Semiconductors, 74HC373D,653 Datasheet - Page 15
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74HC373D,653
Manufacturer Part Number
74HC373D,653
Description
IC LATCH TRANSP OCT D 3ST 20SOIC
Manufacturer
NXP Semiconductors
Series
74HCr
Datasheet
1.74HC373PW118.pdf
(26 pages)
Specifications of 74HC373D,653
Logic Type
D-Type Transparent Latch
Package / Case
20-SOIC (7.5mm Width)
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
2 V ~ 6 V
Independent Circuits
1
Delay Time - Propagation
12ns
Current - Output High, Low
7.8mA, 7.8mA
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Number Of Circuits
8
Logic Family
HC
Polarity
Non-Inverting
High Level Output Current
- 7.8 mA
Low Level Output Current
7.8 mA
Propagation Delay Time
12 ns at 5 V
Supply Voltage (max)
6 V
Supply Voltage (min)
2 V
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-1437-2
74HC373D-T
933715470653
74HC373D-T
933715470653
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
74HC373D,653
Manufacturer:
BCD
Quantity:
51
NXP Semiconductors
Table 9.
Voltages are referenced to GND (ground = 0 V); C
[1]
[2]
[3]
[4]
[5]
11. Waveforms
74HC_HCT373
Product data sheet
Symbol Parameter
t
h
Fig 8.
Fig 9.
t
t
t
t
C
P
f
f
C
V
N = number of inputs switching;
∑(C
pd
en
dis
t
i
o
D
CC
PD
= input frequency in MHz;
L
is the same as t
= output frequency in MHz;
is the same as t
is the same as t
= output load capacitance in pF;
= C
is the same as t
L
is used to determine the dynamic power dissipation (P
= supply voltage in V;
× V
hold time Dn to LE
Measurement points are given in
Propagation delay input (Dn) to output (Qn) and transition time output (Qn)
Measurement points are given in
Pulse width latch enable input (LE), propagation delay (LE) to output (Qn) and transition time output (Qn)
PD
Dynamic characteristics 74HCT373
CC
× V
2
× f
CC
o
2
) = sum of outputs.
× f
THL
PLH
PZH
PLZ
i
× N + ∑(C
and t
and t
and t
and t
TLH
PHL
PZL
PHZ
.
L
.
.
.
× V
Qn output
Qn output
LE input
Dn input
CC
2
× f
Table
Table
o
All information provided in this document is subject to legal disclaimers.
) where:
10.
10.
Conditions
Dn to LE; see
Rev. 4 — 3 September 2010
t
…continued
L
THL
V
V
90 %
= 50 pF unless otherwise specified; for test circuit see
M
t
CC
PHL
V
t
t
W
= 4.5 V
M
TLH
t
10 %
D
PLH
in μW).
V
V
M
M
10 %
Figure 11
90 %
t
TLH
t
THL
t
t
PHL
PLH
74HC373; 74HCT373
Octal D-type transparent latch; 3-state
001aae082
001aae083
Min
4
Typ
-
© NXP B.V. 2010. All rights reserved.
Figure
Max
-
12.
Unit
ns
15 of 26