74LVT16373ADL,118 NXP Semiconductors, 74LVT16373ADL,118 Datasheet - Page 2

• Manufacturer Part Number: 74LVT16373ADL,118
• Description: IC 16BIT TRANSP LATCH D 48SSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVTr

Specifications of 74LVT16373ADL,118

• Logic Type: D-Type Transparent Latch
• Package / Case: 48-SSOP
• Circuit: 8:8
• Output Type: Tri-State
• Voltage - Supply: 2.7 V ~ 3.6 V
• Independent Circuits: 2
• Delay Time - Propagation: 2.1ns
• Current - Output High, Low: 32mA, 64mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Circuits: 2
• Logic Family: LVT
• Polarity: Non-Inverting
• Input Bias Current (max): 4000 uA
• High Level Output Current: - 32 mA
• Low Level Output Current: 64 mA
• Propagation Delay Time: 1.9 ns at 3.3 V
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74LVT16373ADL-T; 74LVT16373ADL-T; 935183110118

FEATURES
QUICK REFERENCE DATA
ORDERING INFORMATION
LOGIC SYMBOL
Philips Semiconductors
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
1998 Feb 19
16-bit transparent latch
3-State buffers
Output capability: +64mA/-32mA
TTL input and output switching levels
Input and output interface capability to systems at 5V supply
Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
Live insertion/extraction permitted
Power-up reset
Power-up 3-State
No bus current loading when output is tied to 5V bus
Latch-up protection exceeds 500mA per JEDEC Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
3.3V 16-bit transparent D-type latch (3-State)
SYMBOL
C
I
t
t
C
PLH
PHL
CCZ
OUT
IN
48
24
25
1
PACKAGES
1LE
1OE
2LE
2OE
1Q0 1Q1 1Q2
1D0 1D1 1D2 1D3
2D0 2D21 2D2 2D3
2Q0 2Q1 2Q2 2Q3
47
13
36
2
Propagation delay
nDx to nQx
Input capacitance
Output capacitance
Total supply current
46
35
14
3
44
16
33
5
1Q3
43
32
17
6
1Q4 1Q5 1Q6
1D4 1D5 1D6 1D7
2Q4 2Q5 2Q6 2Q7
PARAMETER
2D4 2D5 2D6 2D7
41
30
19
8
TEMPERATURE RANGE
40
29
20
9
38
11
–40 C to +85 C
–40 C to +85 C
27
22
SA00044
1Q7
37
12
26
23
C
V
V
Outputs disabled; V
Outputs disabled; V
CC
I
L
= 0V or 3.0V
OUTSIDE NORTH AMERICA
= 50pF;
= 3.3V
2
74LVT16373A DGG
74LVT16373A DL
DESCRIPTION
The 74LVT16373A is a high-performance BiCMOS product
designed for V
This device is a 16-bit transparent D-type latch with non-inverting
3-State bus compatible outputs. The device can be used as two
8-bit latches or one 16-bit latch. When enable (E) input is High, the
Q outputs follow the data (D) inputs. When enable is taken Low, the
Q outputs are latched at the levels of the D inputs one setup time
prior to the High-to-Low transition.
PIN DESCRIPTION
47, 46, 44, 43, 41, 40, 38, 37,
36, 35, 33, 32, 30, 29, 27, 26
4, 10, 15, 21, 28, 34, 39, 45
CONDITIONS
T
2, 3, 5, 6, 8, 9, 11, 12, 13,
14, 16, 17, 19, 20, 22, 23
amb
PIN NUMBER
= 25 C
O
CC
7, 18, 31, 42
= 0V or 3.0V
= 3.6V
48, 25
CC
1, 24
operation at 3.3V.
NORTH AMERICA
VT16373A DGG
VT16373A DL
1Q0 – 1Q7
2Q0 – 2Q7
1D0 – 1D7
2D0 – 2D7
1OE, 2OE
SYMBOL
1E, 2E
GND
TYPICAL
V
74LVT16373A
CC
1.9
70
3
9
Product specification
DWG NUMBER
853-1780 18989
FUNCTION
Data inputs
Data outputs
Output enable
inputs
(active-Low)
Enable inputs
(active-High)
Ground (0V)
Positive
supply voltage
SOT370-1
SOT362-1
UNIT
ns
pF
pF
A