74ALVC573D,112 NXP Semiconductors, 74ALVC573D,112 Datasheet

no-image

74ALVC573D,112

Manufacturer Part Number
74ALVC573D,112
Description
IC OCTAL D TRANSP LATCH 20SOIC
Manufacturer
NXP Semiconductors
Series
74ALVCr
Datasheet

Specifications of 74ALVC573D,112

Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
1.65 V ~ 3.6 V
Independent Circuits
1
Delay Time - Propagation
2.2ns
Current - Output High, Low
24mA, 24mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74ALVC573D
74ALVC573D
935269737112
1. General description
2. Features
The 74ALVC573 is an octal D-type transparent latch featuring separate D-type inputs for
each latch and 3-state true outputs for bus-oriented applications. A latch enable (LE) input
and an outputs enable (OE) input are common to all latches.
When pin LE is HIGH, data at the D-inputs (pins D0 to D7) enters the latches. In this
condition, the latches are transparent, that is, a latch output will change each time its
corresponding D-input changes. When pin LE is LOW, the latches store the information
that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of
pin LE.
When pin OE is LOW, the contents of the eight latches are available at the Q-outputs (pins
Q0 to Q7). When pin OE is HIGH, the outputs go to the high-impedance OFF-state.
Operation of input pin OE does not affect the state of the latches.
The 74ALVC573 is functionally identical to the 74ALVC373, but has a different pin
arrangement.
74ALVC573
Octal D-type transparent latch; 3-state
Rev. 03 — 26 October 2007
Wide supply voltage range from 1.65 V to 3.6 V
3.6 V tolerant inputs/outputs
CMOS low power consumption
Direct interface with TTL levels (2.7 V to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
Complies with JEDEC standards:
ESD protection:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A 115-A exceeds 200 V
Product data sheet

Related parts for 74ALVC573D,112

74ALVC573D,112 Summary of contents

Page 1

Octal D-type transparent latch; 3-state Rev. 03 — 26 October 2007 1. General description The 74ALVC573 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74ALVC573D +85 C 74ALVC573PW +85 C 74ALVC573BQ + Functional diagram Fig 1. Logic symbol Fig 3. Functional diagram 74ALVC573_3 Product data sheet Description SO20 plastic small outline package; 20 leads; body width 7.5 mm TSSOP20 plastic thin shrink small outline package ...

Page 3

... NXP Semiconductors Fig 4. Logic diagram (one latch LATCH LATCH Fig 5. Logic diagram 74ALVC573_3 Product data sheet LATCH LATCH Rev. 03 — 26 October 2007 74ALVC573 Octal D-type transparent latch; 3-state Q mna189 LATCH LATCH LATCH LATCH mna810 © NXP B.V. 2007. All rights reserved. ...

Page 4

... NXP Semiconductors 5. Pinning information 5.1 Pinning 573 GND 10 001aad099 Fig 6. Pin configuration SO20 and TSSOP20 5.2 Pin description Table 2. Pin description Symbol Pin D[0: Q[0:7] 19, 18, 17, 16, 15, 14, 13 GND 10 74ALVC573_3 Product data sheet (1) The die substrate is attached to this pad using conductive die attach material ...

Page 5

... NXP Semiconductors 6. Functional description [1] Table 3. Functional table Operating modes Input OE Enable and read register L (transparent mode) L Latch and read register L L Latch register and disable H outputs H [ HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition L = LOW voltage level ...

Page 6

... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). ...

Page 7

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter I OFF-state output current OZ I power-off leakage supply OFF I supply current CC I additional supply current CC C input capacitance I [1] All typical values are measured at V 10. Dynamic characteristics Table 7 ...

Page 8

... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter t pulse width W t set-up time su t hold time h C power dissipation PD capacitance [1] Typical values are measured the same as t and PHL PLH t is the same as t and t ...

Page 9

... NXP Semiconductors 11. Waveforms Measurement points are given in V and V are the typical output voltage levels that occur with the output load Fig 8. Input Dn to output Qn propagation delay times Table 8. Measurement points Supply voltage 1. 1.95 V 0.5V 2 2.7 V 0.5V 2.7 V 1 ...

Page 10

... NXP Semiconductors OE input Qn output LOW-to-OFF OFF-to-LOW Qn output HIGH-to-OFF OFF-to-HIGH Measurement points are given in V and V are the typical output voltage levels that occur with the output load Fig 10. Enable and disable times Dn input LE input Measurement points are given in The shaded areas indicate when the input is permitted to change for predicable output performance. ...

Page 11

... NXP Semiconductors Test data is given in Table 9. Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance External voltage for measuring switching times. EXT Fig 12. Test circuitry for switching times Table 9. Test data ...

Page 12

... NXP Semiconductors 12. Package outline SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 13

... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 14

... NXP Semiconductors DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 15

... Document ID Release date 74ALVC573_3 20071026 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section • Section • ...

Page 16

... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...

Page 17

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 14 Revision history ...

Related keywords