74LVT162373DL,112 NXP Semiconductors, 74LVT162373DL,112 Datasheet - Page 2

• Manufacturer Part Number: 74LVT162373DL,112
• Description: IC 16BIT TRANSP LATCH 48SSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVTr

Specifications of 74LVT162373DL,112

• Logic Type: D-Type Transparent Latch
• Circuit: 8:8
• Output Type: Tri-State
• Voltage - Supply: 2.7 V ~ 3.6 V
• Independent Circuits: 2
• Delay Time - Propagation: 3ns
• Current - Output High, Low: 12mA, 12mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74LVT162373DL; 74LVT162373DL; 935264163112

FEATURES
QUICK REFERENCE DATA
ORDERING INFORMATION
Philips Semiconductors
1999 Sep 23
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
16-bit transparent latch
3-State buffers
Output capability: +12 mA / –12 mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
Live insertion/extraction permitted
Outputs include series resistance of 30
resistors unnecessary
Power-up reset
Power-up 3-State
No bus current loading when output is tied to 5 V bus
Latch-up protection exceeds 500 mA per JEDEC Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
3.3 V LVT 16-bit transparent D-type latch
with 30
SYMBOL
C
I
t
t
C
PLH
PHL
CCZ
OUT
IN
PACKAGES
termination resistors (3-State)
Propagation delay
nDx to nQx
Input capacitance
Output capacitance
Total supply current
PARAMETER
making external
TEMPERATURE RANGE
–40 C to +85 C
–40 C to +85 C
C
V
V
Outputs disabled; V
Outputs disabled; V
L
CC
I
= 0 V or 3.0 V
= 50 pF;
= 3.3 V
2
DESCRIPTION
The 74LVT162373 is a high-performance BiCMOS product designed
for V
This device is a 16-bit transparent D-type latch with non-inverting
3-State bus compatible outputs. The device can be used as two
8-bit latches or one 16-bit latch. When Latch Enable (LE) input is
High, the Q outputs follow the data (D) inputs. When Latch Enable is
taken Low, the Q outputs are latched at the levels of the D inputs
one setup time prior to the High-to-Low transition.
The 74LVT162373 is designed with 30
the High and Low states of the output. This design reduces the
noise in applications such as memory address drivers, clock drivers,
and bus receivers/transmitters.
CONDITIONS
T
CC
amb
operation at 3.3 V.
= 25 C
O
CC
= 0 V or 3.0 V
74LVT162373 DGG
ORDERING CODE
= 3.6 V
74LVT162373 DL
TYPICAL
74LVT162373
series resistance in both
3.0
70
3
9
Product specification
DWG NUMBER
SOT370-1
SOT362-1
853-2172 22406
UNIT
ns
pF
pF
A