74LVT573BQ,115 NXP Semiconductors, 74LVT573BQ,115 Datasheet - Page 8

• Manufacturer Part Number: 74LVT573BQ,115
• Description: IC OCTAL D TRANSP LATCH 20DHVQFN
• Manufacturer: NXP Semiconductors
• Series: 74LVTr

Specifications of 74LVT573BQ,115

• Logic Type: D-Type Transparent Latch
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Circuit: 8:8
• Output Type: Tri-State
• Voltage - Supply: 2.7 V ~ 3.6 V
• Independent Circuits: 1
• Delay Time - Propagation: 6.3ns
• Current - Output High, Low: 32mA, 64mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Circuits: 8
• Logic Family: 74LVT
• Polarity: Non-Inverting
• Input Bias Current (max): 3000 uA
• High Level Output Current: - 32 mA
• Low Level Output Current: 32 mA
• Propagation Delay Time: 2.5 ns at 3.3 V
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 12 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74LVT573BQ-G; 74LVT573BQ-G; 935285607115

NXP Semiconductors
11. Waveforms
Table 8.
74LVT573_4
Product data sheet
Input
V
1.5 V
Fig 6.
Fig 8.
Fig 10. Data setup and hold times for data (Dn) and latch enable (LE) inputs
M
Qn output
LE input
Qn output
OE input
V
V
0 V
OH
OL
Measurement points are given in
Propagation delays latch enable input (LE) to
output (Qn), and latch enable (LE) pulse width
Measurement points are given in
V
with the output load.
Output enable time to HIGH-state and output
disable time from HIGH-state
Measurement points are given in
Remark: The shaded areas indicate when the input is permitted to change for predictable output performance.
V
V
0 V
0 V
OH
OL
I
Measurement points
V
I
and V
V
M
OH
t
PHL
t
WH
are typical voltage output levels that occur
V
M
t
PZH
V
M
Dn input
LE input
Output
V
1.5 V
V
M
t
M
WL
0 V
0 V
V
V
V
I
I
Table
Table
Table
M
t
PHZ
t
8.
8.
8.
PLH
V
Rev. 04 — 15 September 2008
001aai745
Y
V
M
001aai743
t
su(L)
V
M
V
V
Fig 7.
Fig 9.
t
h(H)
X
OL
+ 0.3 V
Qn output
Dn input
Qn output
OE input
3.3 V octal D-type transparent latch; (3-state)
3.0 V
Measurement points are given in
Propagation delay data input (Dn) to
output (Qn)
Measurement points are given in
Output enable time to LOW-state and output
disable time from LOW-state
V
0 V
OL
V
I
V
t
V
su(H)
0 V
OH
OL
V
I
V
001aai744
M
t
PZL
t
h(L)
V
M
V
V
V
V
M
Y
OH
t
PHL
M
0.3 V
74LVT573
V
Table
Table
M
t
PLZ
© NXP B.V. 2008. All rights reserved.
8.
8.
V
001aai746
X
001aai742
t
PLH
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