N74F280BD,623 NXP Semiconductors, N74F280BD,623 Datasheet - Page 2

• Manufacturer Part Number: N74F280BD,623
• Description: IC PARITY GEN/CHKER 9BIT 14SOIC
• Manufacturer: NXP Semiconductors
• Series: 74Fr

Specifications of N74F280BD,623

• Logic Type: Parity Generator/Checker
• Number Of Circuits: 9-Bit
• Current - Output High, Low: 1mA, 20mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (0.154", 3.90mm Width)
• Number Of Bits: 9
• Logic Family: F
• High Level Output Current: - 1 mA
• Low Level Output Current: 20 mA
• Propagation Delay Time: 10 ns
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 933829010623; N74F280BD-T; N74F280BD-T

Philips Semiconductors
FEATURES
DESCRIPTION
The 74F280B is a 9-bit Parity Generator or Checker commonly used
to detect errors in high speed data transmission or data retrieval
systems. Both Even (
for generating or checking even or odd parity on up to 9 bits.
The Even (
inputs (I
odd number of Data inputs are High.
Expansion to larger word sizes is accomplished by tying the Even
(
final stage. This expansion scheme allows an 81-bit data word to be
checked in less than 20ns.
ORDERING INFORMATION
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
NOTE:
One (1.0) FAST Unit Load is defined as: 20 A in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
1996 Mar 12
High-impedance NPN base inputs for reduced loading
(20 A in Low and High states)
Buffered inputs — one normalized load
Word length easily expanded by cascading
Industrial temperature range available (–40 C to +85 C)
E
9-bit odd/even parity generator/checker
) outputs of up to nine parallel devices to the data inputs of the
14-pin plastic DIP
14-pin plastic SO
0
DESCRIPTION
- I
8
E
) are High. The Odd (
) parity output is High when an even number of Data
PINS
I
0
E
,
- I
8
O
I
8
0
E
I
9
) and Odd (
1
10 11 12 13
I
2
5
I
E
3
I
4
O
) parity output is High when an
O
I
5
) parity outputs are available
6
O
COMMERCIAL RANGE
I
1
6
T
amb
SF00845
V
I
2
7
CC
N74F280BN
N74F280BD
DESCRIPTION
= 0 C to +70 C
I
Parity outputs
4
8
= 5V 10%,
Data inputs
2
PIN CONFIGURATION
IEC/IEEE SYMBOL
74F280B
V
GND=Pin 7
CC
TYPE
T
INDUSTRIAL RANGE
amb
=Pin 14
V
CC
= –40 C to +85 C
I74F280BN
I74F280BD
HIGH/LOW
= 5V 10%,
74F(U.L.)
1.0/0.033
50/33
PROPAGATION
GND
TYPICAL
NC
DELAY
10
11
12
13
I
I
I
O
E
6
7
8
8
9
1
2
4
5.5ns
1
2
3
4
5
6
7
2K
SF00849
O
E
SF00846
14
13
12
10
11
9
8
SUPPLY CURRENT
LOAD VALUE
PKG. DWG. #
1.0mA/20mA
HIGH/LOW
20 A/20 A
Product specification
V
I
I
I
I
I
I
5
4
3
2
1
0
SOT108-1
SOT27-1
CC
TYPICAL
(TOTAL)
5
6
74F280B
26mA
853-0363 16555