74HCT4094N,112 NXP Semiconductors, 74HCT4094N,112 Datasheet - Page 2

• Manufacturer Part Number: 74HCT4094N,112
• Description: IC 8STAGE SHIFT/STORE BUS 16-DIP
• Manufacturer: NXP Semiconductors
• Series: 74HCTr

Specifications of 74HCT4094N,112

• Package / Case: 16-DIP (0.300", 7.62mm)
• Logic Type: Shift Register
• Output Type: Standard
• Function: Serial to Parallel
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Counting Sequence: Serial to Serial/Parallel
• Number Of Circuits: 1
• Logic Family: HCT
• Propagation Delay Time: 43 ns
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-4484-5; 74HCT4094N; 74HCT4094N; 933670410112

Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT4094 are high-speed Si-gate CMOS
devices and are pin compatible with the “4094” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4094 are 8-stage serial shift registers
having a storage latch associated with each stage for
strobing data from the serial input (D) to the parallel
buffered 3-state outputs (QP
may be connected directly to common bus lines.
Data is shifted on the positive-going clock (CP) transitions.
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
ORDERING INFORMATION
See
December 1990
t
f
C
C
PHL
max
SYMBOL
Output capability: standard
I
8-stage shift-and-store bus register
I
PD
CC
f
f
C
V
For HCT the condition is V
i
o
“74HC/HCT/HCU/HCMOS Logic Package Information”
/ t
CC
PD
= input frequency in MHz
L
category: MSI
= output frequency in MHz
(C
PLH
= output load capacitance in pF
P
= supply voltage in V
is used to determine the dynamic power dissipation (P
L
D
= C
V
amb
CC
PD
propagation delay
CP to QS
CP to QS
CP to QP
STR to QP
maximum clock frequency
input capacitance
power dissipation capacitance per package
2
= 25 C; t
V
f
o
CC
) = sum of outputs
2
1
2
n
n
f
r
i
0
= t
PARAMETER
to QP
I
I
f
= GND to V
= GND to V
= 6 ns
(C
L
7
). The parallel outputs
V
CC
2
CC
CC
f
o
) where:
1.5 V
2
.
C
notes 1 and 2
The data in each shift register stage is transferred to the
storage register when the strobe input (STR) is HIGH.
Data in the storage register appears at the outputs
whenever the output enable input (OE) signal is HIGH.
Two serial outputs (QS
cascading a number of “4094” devices. Data is available at
QS
operation in cascaded systems in which the clock rise time
is fast. The same serial information is available at QS
the next negative-going clock edge and is for cascading
“4094” devices when the clock rise time is slow.
APPLICATIONS
L
D
Serial-to-parallel data conversion
Remote control holding register
= 15 pF; V
1
in W):
CONDITIONS
on the positive-going clock edges to allow high-speed
CC
= 5 V
1
15
13
20
18
95
3.5
83
and QS
HC
TYPICAL
74HC/HCT4094
2
) are available for
Product specification
19
18
21
19
86
3.5
92
HCT
ns
ns
ns
ns
MHz
pF
pF
UNIT
2
on