HEF4021BT,653 NXP Semiconductors, HEF4021BT,653 Datasheet - Page 7

• Manufacturer Part Number: HEF4021BT,653
• Description: IC STATIC SHIFT REG 8BIT 16SOIC
• Manufacturer: NXP Semiconductors
• Series: 4000Br
• Type: Not Requiredr

Specifications of HEF4021BT,653

• Package / Case: 16-SOIC (3.9mm Width)
• Logic Type: Shift Register
• Function: Parallel or Serial to Serial
• Output Type: Standard
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Voltage - Supply: 3 V ~ 15 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Counting Sequence: Serial/Parallel to Parallel
• Number Of Circuits: 1
• Logic Family: HEF4000
• Propagation Delay Time: 40 ns
• Supply Voltage (max): 15.5 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V, 5 V, 9 V, 12 V
• Supply Voltage (min): 4.5 V
• Technology: CMOS
• Number Of Elements: 1
• Number Of Bits: 8
• Logical Function: Shift Register
• Operating Supply Voltage (typ): 3.3/5/9/12V
• Package Type: SO
• Operating Temp Range: -40C to 125C
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 15V
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 933372740653; HEF4021BTD-T; HEF4021BTD-T

NXP Semiconductors
Table 8.
P
12. Waveforms
HEF4021B_6
Product data sheet
Symbol
P
D
Fig 4.
Fig 5.
D
can be calculated from the formulas shown. V
Waveforms showing propagation delays for CP and PL inputs to Qn output and Qn transition times
Waveforms showing minimum clock pulse width, set-up time, and hold time for CP and DS.
Dynamic power dissipation P
Parameter
dynamic power
dissipation
CP INPUT
DS INPUT
CP or PL INPUT
Qn OUTPUT
V
V
V
V
DD
DD
SS
SS
V
10 V
15 V
5 V
DD
V
V
V
V
DD
OH
SS
OL
V
Typical formula for P
P
P
P
M
t
D
su
D
D
D
= 900
= 4300
= 12000
V
t
M
V
PHL
Rev. 06 — 27 November 2009
SS
V
M
Y
t
h
= 0 V; t
V
f
V
i
M
f
X
+ (f
i
t
f
t
1 / f
+ (f
i
+ (f
r
= t
clk(max)
o
o
f
o
C
D
C
20 ns; T
L
C
)
( W)
L
t
)
W
L
)
V
V
DD
V
DD
amb
2
DD
2
t
PLH
2
= 25 C.
t
t
where:
f
f
C
V
i
o
(f
DD
= input frequency in MHz,
L
= output frequency in MHz,
o
= output load capacitance in pF,
= supply voltage in V,
C
001aaj060
L
001aae611
) = sum of the outputs.
8-bit static shift register
HEF4021B
© NXP B.V. 2009. All rights reserved.
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